资源列表
uart_send5bytes
- CPLD实现串口发五个字节，有校验，验证可用。注释明了-CPLD realization of the serial transceiver five bytes, verification, validation available. Note clear
DE0_Nano_SOPC_DEMO
- DE0_Nano的DEMO，很不错的，值得学习。这是整个工程-sopc demo of DE0_Nano
N-jishu-fenpin
- N倍奇数分频器源码,可根据需要修改N数字即可-N times odd divider source
sdram-control
- 基于FPGA的SDRAM读写控制程序，由VHDL语言编写-FPGA-based SDRAM read and write control program, by the VHDL language
33-square-root
- 使用VHDL语言实现33位平方根进位选择加法器，能满足在500M时钟下正确工作，使用DB测试，并通过前仿。-Using VHDL language 33 square root carry select adder, to meet in the 500M clock work correctly, use the DB test, and through imitation.
simple_spi
- 广泛使用的spi总线描述，里面详细的列出了其协议，以及相应的verilog代码实现-Spi bus descr iption widely used, which is a detailed list of their agreement, and the corresponding verilog code implementation
vhdl-code-for--A-HIGH-SPEED-SYMMETRIC-CROSSBAR-SW
- vhdl code for A HIGH SPEED SYMMETRIC CROSSBAR SWITCH-vhdl code for A HIGH SPEED SYMMETRIC CROSSBAR SWITCH
clock
- 可以當電子時鐘，有計時、調時還可以設鬧鐘，並且有鬧鈴-When the electronic clock timing, tune while you set the alarm clock and alarm
Verilog_divid
- vhdl语言描述传统除法器，传统乘法器的改进，从原理到实现的传统除法器-vhdl language to describe the traditional divider, the improvement of traditional multiplier principle to achieve the traditional divider
test_goldschmidt.vhd
- code to test a goldschmidt divider-code to test a goldschmidt divider
RSA
- programme qui decrit l algorithme de chiffremment RSA
THE-FIR-Base-on-FPGA
- 基于fpga的FIR滤波器实现，程序为11阶滤波器实现的源代码-Fpga-based FIR filter implementation, the source code