资源列表
zuihou
- 数字时钟，有校正、闹钟、复位灯一些功能-Digital clock, correction, some of the features of the alarm clock, reset lamp! ! ! ! !
Ptxd
- 模拟RS-232串口产生周期串口数据，可以根据需要修改周期参数，及时钟参数，代码可以直接用来产生需要波特率的通讯模拟数据。-Analog RS-232 serial port generates cycle serial data, based on the need to modify the cycle parameters, and clock parameters, the code can be directly used to generate analog data communi
jiaozhi_1024
- 用VHDL语言实现按字节交织，交织深度为4.每组256字节-Block interleaver
dab1814114c3
- 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Descr iption ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route
Rapid-Prototyping-of-Digital-Systems
- 一本关于数字系统的书，可以帮助大家快速入门-Rapid Prototyping of Digital Systems
12864
- FPGA控制lcd12864，基于VHDL语言，适合初学者入门之用-realization of lcd12864 control based on FPGA
DSP
- 用matlab的simulink功能进行DSP设计-Using matlab simulink function DSP design
VHDL-Programming-by-Example
- 一本介绍用VHDL写的一些关于FPGA的例程-McGraw Hill VHDL Programming by Example
KCPSM6_Release5_30Sept12(Virtex6)
- XIlinx Virtex-6 （Spartan6及7系列）的PicoBlaze的源代码（官网转载），与用于Virtex2、Spartan3的不一样！-Xilinx Virtex-6 (Spartan6-and 7 series), the PicoBlaze the source code (the official website reproduced) with for Virtex2, the Spartan3' s not!
jiaozhi_64
- VHDL语言实现按字节块交织，实现每64字节进行一次交织。-The VHDL language byte block interleaving, once every 64 bytes intertwined.
BARK-xuhuanmafinal
- 简单的quartus循环码设计，中间加入了BARK码帮助同步。希望对大家有所帮助。-Simple the quartus cycle code design, joined in the middle BARK code to help synchronize. I hope to be helpful to everyone.
scramble_m_que
- 产生19级m序列，实现加扰和解扰的全过程。-19 m sequences, the scrambling process