资源列表
ep1c6_21_uart
- 串口发送接收测试模块，FPGA基础实验学习，欢迎大家下载。-Serial receiver test modules, FPGA-based experiential learning, welcome to download.
FFT_vhdl
- 基于fpga的fft编程的程序 基于fpga的fft编程的程序 基于fpga的fft编程的程序-Fpga fft programming-based program based on fpga fft programming procedure based on fpga fft programming procedure based on FPGA FFT programming procedures
DDS_SYS_CLK100M
- 基于FPGA的信号源设计，100M时钟，32位相位累加，能产生正玄波、方波，三角波，锯齿波，频率可调，频率范围0.03HZ-15MHZ。-FPGA-based signal source design, 100M clock, 32-bit phase accumulation can produce sine wave, square wave, triangle wave, sawtooth, adjustable frequency, the frequency range 0.03 Hz
uart-project
- uart verilog zzpoifeow fwpoep wf wpo fpw pdfikwpoe e opfewiepfow [efkpow f pkw[fpkdw[kef[w fkepowkf[ok[ew f[pekwp fpoefi[wie-UART verilog
config
- cher la MPPT d un panneau photovoltaï que -chercher la MPPT d un panneau photovoltaï que
revisions-sur-la-conception-VHDL
- cours VHDL comment on va apprendre la programmation vhdl
defuzzification
- cher la MPPT d un panneau photovoltaï que -chercher la MPPT d un panneau photovoltaï que
fuzzification
- cher la MPPT d un panneau photovoltaï que -chercher la MPPT d un panneau photovoltaï que
fuzzy_rulebase
- cher la MPPT d un panneau photovoltaï que -chercher la MPPT d un panneau photovoltaï que
1_wire
- 基于niosII设计的ds18b20控制温度设计，能在开发板上实现。-Based on niosII design ds18b20 temperature control design can be achieved in the development board.
parity
- Eight bit Parity generator in verilog with Mux Generador de paridad de ocho bits con multiplexor
Control_Display
- Controlador de display siete segmentos en verilog El archivo contiene selector decodificador multiplexor y archivo para simulacion Sevent segment dispay controler in verilog for basys nexys2 nexys3 fpga boards This file have a decoder, selector