资源列表
dangeanjian
- 单个按键控制数码管加 通过对单个按键的控制使数码管自动增加-Single button control digital tube plus single button control digital tube automatically increase
yidongshuzi
- 移动显示数字 四位数码管上显示四位数字，通过对时钟的控制，使数字自动流动-Mobile Display Digital four digital tube display four-digit digital automatic flow through the control of the clock,
liushuidanwei
- 流水灯加单位数码管 流水灯自动来回流动，单位数码管自动计数-Light water units plus digital tube light water flow back and forth the unit digital tube automatic counting
anjiandanwei
- 按键通过单位数码管显示 10个按键，不同的按键数码管上显示不同数字-Key unit digital tube display 10 keys, key digital tube display different figures
the-taxi-meter
- 利用MAX plus10.2对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。-The MAX plus10.2 the design of the taxi meter VHDL code simulation, and FPGA digital experimental system To implement the control. This is the decoding module
shuzipaidui
- 3*3按键控制多位数码管，四位数码管上显示数字由大到小，按键控制移位-3* 3 keys to control a number of digital control, four digital tube display digital descending, key control shift
zuojiayoujian
- 四位数码管左边两位自动增加，右边两位自动减少-Four digital tube left two increases, the right two automatically reduces
xapp199
- writing efficient testbenches
VHDL-to-design-detector
- 用VHDL语言设计一个序列“111010”的检测器和该序列的发生器-VHDL language " 111010" to design a sequence detector and the sequence generator
adsawfd
- 用Verilog HDL设计3线-8线译码器，ena是译码器的使能控制端，当ena=1时译码器工作，ena=0时译码器被禁止，8个输出均为高电平 用Verilog HDL设计具有三态输出的8D锁存器。-3-to-8 line decoder, ENA is designed using Verilog HDL the decoder enable control terminal, when ena = 1 time decoder, ENA = 0 time decoder is disa
ewgweg
- 5959计时器及用数码管显示出来其中包括顶层程序和子程序-5959 timer and digital display including the top-level routines and subroutines
Digit_sys_proj-tbird
- T-bird LED by modelsim 6.5e