资源列表
weitebi_notes
- 维特比译码 ，说明比较详细， 用于卷积的译码，很不错-Viterbi decoding, a more detailed descr iption
shuzishizong
- 通过按键实现数字时钟的时间调节和 闹钟调节 -Digital clock alarm clock is adjustable
jiaotongdeng
- 状态机实现十字路口的交通灯红黄绿 代码中用八位的led高三位灯分别表示a路口的红黄绿低三位表示b路口的红黄绿-State machine to achieve the crossroads of traffic lights red yellow and green code with eight high three LED lights denote a junction of red, yellow, and green the lower three b junction of red
one
- 做数字频率计所需要的系数为6.5的分频器相关编程作为参考-Need to do the digital frequency meter factor of 6.5 as a reference divider programming
FFT_64points
- 64点的 FFT verilog,它是串行计算的，工作频率不到100M，计算速率很高，里面的层次很清晰。-64-point FFT verilog serial computing, the operating frequency of less than 100M, the calculated rate is high, the level inside is very clear.
Viterbi-verilog-codes
- viterbi的无线局域网802.11协议接收端重要的一步。该资料为viterbi的verilog代码，它占用的资源相对比较低，而性能又高。-the viterbi wireless LAN 802.11 receiving end the important step. The viterbi verilog code, it takes up resources is relatively low, and high performance.
wwj
- 基于FPGA的VGA接口时序 分辨率 640*480 源代码-Based on the source code of the FPGA VGA interface timing resolution 640* 480
hdl
- 该资料是HDL语言的入门资料，讲解了verilog语法，以及如何综合，布局布线，设置约束等。内容非常详细。-The data is the HDL language introductory information, explain the Verilog syntax, and how integrated placement and routing, set constraints. Very detailed.
CD1_OV7725_DISPLAY_SAVE
- 基于FPGA的CMOS图像传感器（OV7725）显示并保存图像-FPGA-based CMOS image sensor (OV7725) and save the image
square-root
- simulink/matlab 实现求实数平方根-using simulink to calulate the sequare root of the integer
CD1_OV5620_DISPALY
- 基于FPGA的CMOS图像传感器（OV5620）显示图像-FPGA-based CMOS image sensor (OV5620) image
CD1_MT9D001_DISPALY_SAVE
- 基于FPGA的CMOS图像传感器（MT9D00）显示并保存图像-FPGA-based CMOS image sensor (MT9D00) and save the image