资源列表
e2prom_rd
- Verilog HDL 读取EEPROM项目的详细构建-Verilog HDL EEPROM read the detailed construction
SDRAM
- Verilog HDL 语言构建SDRAM 控制器的详细方案设计-SDRAM controller Verilog HDL language construct detailed program design
TFT_FullDisp_V2.0
- Verilog HDL 语言构建驱动TFT LCD显示屏的详细方案设计-Verilog HDL language construct drive TFT LCD displays detailed program design
VGA
- Verilog HDL 语言驱动VGA显示器的详细方案设计-Verilog HDL language driver VGA display detailed program design
UartRecv
- FPGA Verilog HDL 语言构建串口接收器的详细方案设计-FPGA Verilog HDL language construct serial receive a detailed program design
LED
- 控制led发光的Verilog代码，实现流水灯的效果。-Control led light Verilog code, to achieve the effect of light water.
KEYBOARD
- 用Verilog实现的按键检测及消抖程序代码，工程中很有实用价值。-Achieved using Verilog key detection and debounce code, works great practical value.
D-flip-flop
- D 触发器的描述 寄存器的行为 描述 -D flip-flop registers describe the behavior described in the behavior described register
24CIC
- 基于fpga的抽取CIC滤波器设计,采用verilog编写，24抽取,仿真通过-Fpga-based CIC decimation filter design using verilog written, 24 extraction
interp_24_cic
- 基于fpga的插值CIC滤波器设计,采用verilog编写，24倍插值,仿真通过-Fpga-based interpolation CIC filter design using verilog write, 24x interpolation, through simulation
FIR
- 基于fpga的FIR滤波器设计,已通过modesim仿真结果正确,verilog编写-Fpga-based FIR filter design, has passed modesim simulation results are correct, verilog prepared
hsk4571_clock
- 数字时钟 VHDL实现，可调节时分秒，在QUATTUS||9.0下编写，可在9.0及以上版本运行并下载，芯片为Altera的Cyclone3 EP3C8T1-Digital clock VHDL realization, minutes and seconds can be adjusted in QUATTUS | | 9.0 under preparation, can be run in the 9.0 and above versions and download, chips for