资源列表
PPS
- 脉冲宽度可配置，输出不同脉宽值，启动后输出-The pulse width can be configured with different pulse width, output value
leds
- leds, vhdl spartan 3 nexys2
fp24_prj
- 这是我利用Verilog编写的一个时钟计数器，包括了时钟分钟和秒，结构简单，功能细化，而且我也将仿真结果放在该压缩文件中，通过下载到FPGA的板子当中就可以实现计数，希望对初学FPGA的同学有帮助-This is what I use Verilog prepared a clock counter, including the clock minutes and seconds, simple structure, function refinement, and I will also be
player
- 这是我利用Verilog hdl语言写的关于音乐播放器的程序，其中还包括了仿真结果，该播放器播放的是梁祝，希望对学习Verilog hdl的同学有所帮助-This is what I use Verilog hdl language program written on the music player, which also includes the simulation results, the player is Butterfly, I hope to learn Verilog hdl
maxii_pwm_restored
- 一种PWM波形产生器，可以调节脉冲宽度，频率可调。-One kind of PWM waveform generator, you can adjust the pulse width, frequency adjustable.
claadder
- 4 Bit Carry Look Ahead Adder in Verilog.
bcdadd
- 4-Bit BCD Adder in Verilog
bcdsubtract
- 4-Bit BCD subtract in Verilog
multiplier
- 4x4 multiplxer in verilog
fundamentals-of-digital-logic-with-verilog-design
- fundamentals of digital logic with verilog design
iic
- verilog语言，iic通信，led显示-verilog language, iic communications, led display
johnson
- verilog语言,johnson计数器的设计-johnson counter