资源列表
PDIUSB
- 用VHDl语言实现USB与FPGA接口模块代码-VHDl language with USB and FPGA Interface Module code
my_uart_top
- UART串口传输，参考别人写的，大家修改下就可以用，欢迎参考。-UART serial communication
LCD1602
- VERILOG 语言写的1602液晶屏显示，大家相互学习 相互参考-VERILOG language
23LCD_1602_DISPLAY
- 基于altera公司的fpga的lcd1602显示的源码模块。-Source lcd1602 display module based on fpga altera company.
27_red_light_display
- 基于altera的fpga的红外遥控解码，数码管显示数据的模块。-Altera fpga-based company s infrared remote control decoding, digital display module data.
24_LCD12864_DISPLAY
- 基于altera公司的fpga的lcd12864显示字符汉字的模块，模块接口简单易于复用。-Altera fpga-based company s lcd12864 display kanji character module, the module interface is simple and easy to reuse.
TimingSyn
- MIMO_OFDM系统时间同步方法，基于CAZAC序列-MIMO_OFDM system time synchronization method based CAZAC sequence
86.usb-blaster-win7
- ALERA的USB blaster 驱动，实测win7 64位系统可用。使用方法：更新驱动指向解压后的文件夹接口-ALERA the USB blaster driver, measured win7 64-bit systems available. Use: Updated file folder after extracting the driver to point interfaces
11122604338152
- 用FPGA驱动LCD显示的VHDL程序，URAT VHDL程序与仿真-Driven LCD display with FPGA VHDL program
21d_ask_tz
- 数字信号形式实现模拟2ASK的调制解调功能（模拟信号抽样量化以正弦波载波形式输出）-2ASK digital signal form of analog modulation and demodulation functions (quantized analog output signal is sampled in the form of a sine wave carrier)
2FSK_tiaozhi
- 自己写的一个队2FSK模拟调制的程序（一正弦载波形式输出，抽样量化了），绝对跑得出-To write a team 2FSK analog modulation procedures (a sinusoidal carrier in the form of output, sampling quantified), definitely run out
8-bit-RISC_CPU
- 8位RISC_CPU设计的verilog源码以及工程文件、测试数据文件。在modelsim 10.1d下验证成功，打开工程文件即可使用。-8 RISC_CPU design verilog source code and project files, test data files. In modelsim 10.1d validation is successful, open the project file can be used.