资源列表
FIFO
- 先入先出FIFO，用QUARTUS进行仿真-FIFO FIFO, the simulation with QUARTUS
WriteEfficientTestBenches
- TEST BENCHES FOR SIMULATION ARE VERY IMPORTANT FOR THE FINAL OUTCOME OF VERIFICATION DESIGN. WRITING EFFICIENT TEST BENCHES HELPS IN SIMULATING EFFICIENT DESIGNS
AccelrateDesignPerformance
- FPGAs related material to accelerate design modules
DDS
- 分析了 中流水线结构及输入数据在其中移动的特点 提出了一种 流水线结构 给出了实现的方法并作了仿真 分析了对 电路性能的改进方案-DDS
RS232send
- 用Word文档描述了RS-232模块的发送。-With the Word document describes the RS-232 module to send.
yiweiDCTbianhuan
- 一维DCT变换的Verilog HDL源程序，在ISE中已经通过编译，可以参考里面的文档。-One-dimensional DCT transform Verilog HDL source code, in the ISE has been through the compilation, you can refer to inside the document.
digitalpaobiao
- 用Verilog HDL语言编写的数字跑表源程序，已经通过综合编译及仿真。-With the Verilog HDL source code written in digital stopwatch has been through a comprehensive compilation and simulation.
UART
- UART FOR VHDL hoping that it can give you a hand.
viterbi5
- implemented viterbi in vhdl
risc8
- 简单的RSIC8，实现简单的CPU功能，可以提供大家学习-Simple RSIC8, to achieve a simple CPU features, can provide them to learn from
Writing_Testbenches_Functional_Verification_Of_Hdl
- 本书作者为KLUWER，详细介绍了TESTBENCH程序的编写原理和技巧-The author of this book KLUWER, details the procedures for the preparation of TESTBENCH principles and techniques
Principles_of_Verifiable_RTL_Design
- 本书详细讲解了可验证的RTL级代码的原理，为编写RTL仿真测试程序提供了理论基础-This book gave a detailed RTL-level code verifiable principles for the preparation of RTL simulation test program provides a theoretical basis for