- RMIsample 一个rmi例子程序
- INSPROC_INSERT_A1A1 数据库存储过程
- On-Line_MCMC_Bayesian_Model_Selection This demo nstrates how to use the sequential Monte Carlo algorithm with reversible jump MCMC steps to perform model selection in neural networks. We treat both the model dimension (number of neurons) and model parameters as unknowns. The derivation and details are presented in: Christophe Andrieu
- router_calc 根据一个有权的无向图生成指定结点（路由器）的路由表设有结点N
- demo 此程序是控制台应用程序
- SVD C算法 TXT格式
资源列表
fuyongqi
- vhdl实现解复用器的功能，16位，高效移植性好-vhdl implementation demultiplexer function 16-bit, high efficiency and good graft
adder
- 用vhdl实现加法器的功能，程序简介高效，移植性强-Vhdl adder with the realization of the function, procedures for efficient, portable and strong
muc_cpld
- 51单片机与CPLD的总线通讯程序，简单，实用，内附单片机与CPLD引脚连接原理图。-51 MCU and CPLD bus communication procedures, simple, practical, enclosing the MCU and CPLD pin connections diagram.
CT_Temp
- arithmetic shift operation
FPGAebook
- FPGA入门级的教程，夏老师的，讲解比较清楚，-FPGA entry-level tutorials, summer teacher to explain more clearly, He He
m1_core.tar
- 一个小巧的mips处理器，verilog写的，大家可以-A small mips processor, verilog written, we can see
mlite.tar
- 很强大的mips处理器，用verilog实现的-A very strong mips processor implemented using verilog
s4_vga
- xilinx3s400开发板设计实例，买开发板带的，学习不错-xilinx3s400 development board design example, bought with a development board, and to learn good
my_vix0903
- 基于Xilinx FPGA 的Spartan3 实现的VXI接口-FPGA VXI interface
converter(D-B)
- 用移位快速实现10进制转2进制，无需除法器-quick converter
stopwatch
- 基于vhdl的数字秒表，计时精度为1/100秒，最长计时时间为59分59.59秒；设有复位开关、起停开关；验证可用。-On vhdl digital stopwatch, timing accuracy of 1/100 seconds, the longest time time of 59 minutes 59.59 seconds with reset switch, start-stop switches validation is available.
clock
- 基于vhdl的数字钟,分别由6个数码管显示24小时、60分钟、60秒的计数显示；设有校时、校分、秒清零校正功能，分别由3个按键控制；验证可用。-On vhdl digital clock, respectively, by 6 digital tube display 24 hours, 60 minutes, 60 seconds of the count display with school hours, school hours, seconds, cleared correction