资源列表
Convolutionalencoder
- 应用VHDL语言实现的卷积编码器的应用程序-Application of VHDL language implementation of the convolutional encoder applications
div
- verilog任意分频电路实现，仿真效果非常好-div dclk
timing_ctrl
- 接收时序控制器的verilog描述，及仿真波形。-Receive timing controller verilog descr iptions, and simulation waveforms.
graycnt_14
- 14位格雷码计数器的verilog描述及仿真波形-14-bit Gray code counter verilog descr iption and simulation waveforms
dff_clk
- 简单的D触发器的Verilog描述及，仿真波形-A simple D flip-flop in Verilog descr iption and simulation waveforms
8051
- USB_VHDL USB文件 大家可以参考一下-USB_VHDL USB file you can refer to what
EliminateGlitch
- 通用消除窄脉冲和最大脉冲宽度判断,用于防止外部干扰导致通讯异常,硬件EMC等-GM to eliminate narrow pulses and maximum pulse width to determine, for the prevention of external interference caused abnormal communications, hardware, EMC, etc.
verilog_sample
- example code verilog for clock
EP1C3_12_3_VGA
- 彩条显示，可以实现横竖和水平的显示，副有源程序-Color Bar shows that can be achieved if they had, and the level of the display, the Deputy has source code
VerilogHdlPracticeAndSystemDesign
- 本RAR包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。-The RAR includes " Verilog-HDL Practice and Application of system design," a book full of examples, all passed validation. Ch
Microchip_16C57
- 全球最大的MCU设计公司Microchip 的16C57, 指令完全兼容的clone版本 一并附上说明文件与组合语言测试档-The world largest MCU design Microchip 16C57, fully compatible with the clone version of the directive be accompanied by documentation and assembly language test file
4by4
- 4输入，4输出，clos网络所用，有利于连接处理器和处理器，处理器和存储器传输数据。-4 inputs, 4 outputs, clos network use is conducive to connecting the processor and processor, processor and memory to transfer data.