资源列表
IC035os142_min_bestcase
- 数字电路设计，基本单元逻辑综合库，Worsst case 低温高速条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case conditions of high temperature slow libraries, available dc_shell environment called for RTL synthesis.
IC035os142_typ
- 数字电路设计，基本单元逻辑综合库，Worsst case 室温典型速条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case temperature conditions typical speed database available dc_shell environment called for RTL synthesis.
IC035os142_min_minuse
- 数字电路设计，基本单元逻辑综合库，Worsst case 负温度，极端条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case negative temperature, extreme conditions, libraries, available dc_shell environment called for RTL synthesis
sopc_seg_2c20
- 基于SOPC实现数码管的动态扫描显示 四位一体数码管-Based on SOPC implementation of digital control of dynamic scanning display
Watch
- 秒表功能电路,实现起动、停止等秒表计时功能。-Stopwatch function circuit, start, stop, etc. stopwatch function.
I2C-code
- I2C总线协议 Verilog源代码.试过，没有错误！可以直接使用-I2C bus protocol Verilog source code. Tried, no errors! Can be used directly
Calender
- 万年历，可以准确统计并显示当前的年月日等日期时间-Calendar, you can have accurate statistics and displays the current date and time date etc.
ALU
- 8位ALU的设计，学习使用vhdl元件和包集设计-8-bit ALU design, learning to use vhdl components and package design
seqdet_5
- 本程序是5位序列检测器的Verilog源代码,已经过上机运行检测。-This program is five sequence detector Verilog source code, has been detected on the machine running.
fifo_ip
- 本程序是利用ise平台提供的IP核设计出的fifo，通过过上机运行检测。-This procedure is to use ise platform provides IP core design a fifo, passed through the machine running the test.
ram_ip
- 本程序是利用ise平台提供的IP核设计出的ram，已通过上机运行检测。-This procedure is to use ise platform provides IP core design of the ram, has passed the test on the machine running.
rom_ip
- 本程序是利用ise平台提供的IP核设计出的rom，通过上机运行检测。-This procedure is to use ise platform provides IP core design out rom, through testing on the machine running.