资源列表
SCHK
- ise13.2环境下VHDL编写的8位序列检测器+仿真波形-ise13.2 environment in VHDL 8 sequence detector+ simulation waveforms
SHFT8_BC
- ise13.2环境下VHDL编写8位并入串出移位寄存器+仿真波形-ise13.2 environment, VHDL, 8 String into a shift register+ simulation waveforms
bw_scoresource
- This the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.-This is the bowling score source code. Edit tool is xilinx corp ISE. I used the Modelsim for simulation.
laboratory1_1
- DE2指导实验之实验1第一部分 具体实验指导书（英文版）-Instructed Excises 1.1 of DE2
M12
- VHDL硬件描述语言实现M12序列，可以用作白噪声，码率可调-VHDL hardware descr iption language M12 sequence can be used as white noise, adjustable rate
Ram_FIFO
- VHDL硬件语言实现FIFO，管道,经过测试，很好用-VHDL hardware language FIFO, pipe
pjt
- NIOS-II中PIO模拟的IIC驱动控制MT9M034摄像头-PIO simulated IIC driver control MT9M034 camera based on NIOS_II core
cordic
- VHDL实现cordic算法，精确度非常高，模块化设计，带显示功能-VHDL implementation cordic algorithm, a very high accuracy, modular design, with display function
ep1c12_32_vga
- 完整的VGA时序及其彩条显示，棋盘格显示，注释完整-Complete VGA timing and color bar display, checkerboard display, annotate complete
multiclock
- 以VHDL为基础的多功能数字钟的实现功能程序，包括时钟，闹钟，计数等功能。-In VHDL-based implementation of multi-function digital clock procedures, including clock, alarm clock, counting and other functions.
god
- This paper presents a novel robust number theoretic transform called inverse Gray Robust Symmetrical Number System (IGRSNS) and proposes its application for CDMA systems. The transceiver structure for three moduli IGRSNS-CDMA with one redunda
IC035os142_max_worsecase
- 数字电路设计，基本单元逻辑综合库，Worsst case 高温慢速条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case conditions of high temperature slow libraries, available dc_shell environment called for RTL synthesis.