资源列表
frm_sync
- 此程序为帧同步程序，采用状态机的VHDL描述方式编写。-This procedure for frame synchronization procedures, using the state machine to prepare the way VHDL descr iption.
sign_det
- 此程序为符号检测的VHDL程序，用于检测输入数据的最高位符号。-This program is a symbol detection VHDL program for detecting the most significant bit of input data symbols.
jpegencode
- Verilog源码，实现jpeg图片的编解码,内附代码说明文档。-verilog source code to realize the encodeing and decodeing for JPEG
mux16
- 16*16位的乘法器 ， 包含仿真文件-16* 16-bit multiplier, including simulation files! ! ! ! ! ! ! ! ! !
vhdl-code-for-carwash
- automatic car wash system using verilog hdl where car moves from one state to another state for washing based on time intervel
testrom
- My Uploaded Code to test ROM using VHDL.
mux_4
- Uploaded Source code to design and implementation Multiplexcer using VHDL
Reg_4bit
- Uploaded code to design 4 bit register.
ADDER_4_BIT
- implement 4 bit add using vhdl
full_adder
- design full adder by vhdl
sourceCODE
- binary to grey grey to binary 8x3 encoder 2x4 decoder etc- binary to grey grey to binary 8x3 encoder 2x4 decoder etc..
lzrw1-compressor-core_latest.tar
- Lzrw1 压缩算法。spatan6上运行，有完整的仿真环境和代码testbench-Lzrw1 compression algorithm. runs on spatan6, a complete simulation environment and testbench code