资源列表
CRC
- CRC循环校验码的生成。文件里是（40，32）的校验码生成电路，采用串行输入、串行输出的方式。-CRC checksum generation cycle. File is (40,32) of the check code generation circuit, the use of serial input, serial output mode.
FPGA_SOPC_starter
- 非常好的fpga sopc编程入门书籍 非常适合新手进行学习-Fpga sopc very good introductory programming book is ideal for beginners to learn
CRCDecoding
- CRC检错程序。只能检错不能纠错。（40,32）的分组码检错，反馈函数：x8+x7+x4+x3+x+1-CRC error detection process. Not only error detection correction. (40,32) and block code error detection, feedback function: x8+ x7+ x4+ x3+ x+1
ovi.verilog.lrm.1.0
- Original rev 1.0 VerilogHDL Language Reference Manual -Original rev 1.0 Verilog Language Reference Manual
LDPC
- 基于quqrtus2的vhdl语言描述的LDPC的源程序，可以进行时序仿真》-ee
pci32lite_oc
- PCI 32bit Slave Verilog 代码-PCI 32bit Slave Verilog code
ddr
- DDR SDRAM 控制器 VHDL代码，可支持32bits数据总线-VHDL code for DDR SDRAM controller, supporting 32bits data bus
simple_spi_top
- 简单的SPI接口控制器代码。Verilog-A simple SPI interface controller code. Verilog
CPU
- 一个完整的流水CPU设计，quartus平台，Verilog实现-CPU design a complete water, quartus platform, Verilog realization
chuankou
- 实现串口通信:包括发送，接收，时钟以及顶层模块-function of Serial Comunications
chengfaqi.doc
- 设计一个两个5位数相乘的乘法器。用发光二极管显示输入数值，用7段显示器显示结果。乘数和被乘数分两次输入(verilog语言实现)-Design a multiplier of two 5-digit multiplication. Enter the value with the light-emitting diode display, with 7-segment display shows the results. Multiplier and the multiplicand input
fir
- 11阶的FIR 数字滤波器-11-order FIR digital filter