资源列表
circle
- VHDL routine to draw a circle using the midtpoint algorithm.
BeijingUniversityTutorialforVerilog
- Verilog超详细教程，北大微电子系硬件设计入门教程。-Super detailed tutorial Verilog, hardware design, Department of Microelectronics, Peking University Tutorial.
DE2_lab_exercises
- Altera DE2 原装光盘附带 案例教程 手把手教 十个实验 verilog hdl/vhdl-DE2_labs_ exercise with verilog/vhdl
m_sequencer
- m序列发生器，长度可以变化，此处使用长度为40 的移位寄存器。反馈函数使用的是：x40+x5+x4+x3+1-m sequence generator, the length can be varied. here the length of the shift register is 40. Feedback function : x40+ x5+ x4+ x3+1
i2c_core_v02
- I2C FPGA代码，支持master和slave-I2C FPGA code to support master and slave
das3580sch
- das3580开发板原理图，■ Altera CycloneII EP2C8Q208C8N 的FPGA器件； ■ EPCS4 – 4Mbit 串行配置器件； ■ JTAG和AS双模式下载口； ■ 512Kbyte 10ns级SRAM器件构成双数据通道； ■ Cy7c68013a_128axc高性能USB2.0控制芯片；-das3580 development board schematics, ■ Altera CycloneII EP2C8Q208C8N the FPG
DlFIFO
- Fifo for everyone :)
barrelshifter
- barrelshifter which shifts all types of shifts like left,right,logical.
VHDL
- 是一本介绍VHDL 和VHDL 编程的书籍-Is an introductory programming books VHDL and VHDL
clkdivverilog
- 用VerilogHDL实现一个分频器，程序已经通过EPM240测试-With VerilogHDL implement a separate frequency device, the program has passed EPM240 test
hdb3
- verilog的HDB3编码设计，求点数
crc16_finished
- 使用Quartus II软件开发，编程语言为Verilog，实现的是FPGA源代码-Using the Quartus II software development, programming languages Verilog, FPGA source code to achieve the