资源列表
FPGA-source-code-in-IRIG_B-Design
- FPGA在IRIG_B码源设计中FPGA source code in IRIG_B Design-FPGA source code in IRIG_B Design
instruction_decode_v
- MIPS 5 stage pipeline, this file is for instruction decode. you can use it to place in pipline. this has been used in a study lab.
shiboqi
- 虚拟仪器 虚拟示波器 labview初学者的参考资料~-Virtual Instruments virtual oscilloscope labview reference for beginners ~
VHDL
- 计算器实现 功能简单容易实现 可自我调试至更强大性能，不喜勿下-Calculator features simple and easy to achieve self-commissioning to a more powerful performance, do not like not under
sipo_reg5
- VHDL语言描述具有同步清零的5位串行输入并行输出移位寄存器代码-VHDL language to describe the clearing of 5 with synchronous serial input parallel output shift register code
AnApproachBasedonFPGAtoAccelerateAccomplishingReco
- 提出一种在 FPGA 上实现发射光谱层析技术 SIRT算法时 ,在原有资源不变的情况下 ,加速系统运算的方法。该方法把矩阵分块理论的数学原理和 FPGA 具有并行运算能力的优势有机结合 ,使运算速度有效提升。-An approach based on FPGA to accomplish Simultaneous Iterative Reconst ruction Technique (SIRT) of Emis2 sion Spect ral Tomography ( EST) is pr
sys_cpt
- 10.0 quartus 的破解文件，把这个文件替换就可以了 -10.0 quartus the crack file to replace the file on it
cpu_0
- cpu core!! cpu proccesor!
UART_VHDL
- 特别适用于TI C6000 DSP扩展UART的VHDL源代码。-a VHDL source code specially for TI C6000 DSP to extend UART
a
- booth multiplier vhdl code
b
- vhdl code of multiplier