资源列表
ifir_64
- verilog hdl, quartus.64阶的简单回声抵消器，采用的是基本的LMS算法，简单改进，可用于初期了解。功能背景是对通信领域中，比如打电话时自己的声音到达对方经对方环境多径反射又传回自己这边，即回声。为将回声消除采用回声抵消装置。-64 steps a simple echo canceller is used in the basic LMS algorithm, a simple improvement, can be used for the initial understa
password
- password vhdl代码 用于basys2板子-password for basys SJTU STUDENTS
duogongnengzhong
- 多功数字钟 时间可调，校准时间，年月日，闹钟-Adjustable multi-functional digital clock time, calibration time, date, alarm clock
dds_mul
- 简单的多周期dds的verilog编程，出来一个正弦波，可任意改变频率字-Simple multi-cycle dds verilog programming, out of a sine wave, the frequency can be arbitrarily changed words
smg
- 对某一引脚高电平计时并用三位数码管显示程序，每秒钟更新一次，quartus ii开发环境，verilog语言编程-Timing in response to a pin of the high level duration with three digital tube display .Quartus_II software development environment and Verilog language preparation
rtl.tar
- This RTL of Router by uisng verilog-This is RTL of Router by uisng verilog
wehu
- This is an important notes on system verilog from testbench.in
mouse
- Mouse using vhdl language
jieshoufasong
- 实现FPGA和PC机之间的通信。PC机发送的数据可以通过FPGA显示在数码管上；FPGA通过按键发送的数据可以显示在PC机的串口调试助手上。-Communication between the FPGA and the PC. PC sends the data can be displayed through the FPGA digital tube FPGA through the button to send the data can be displayed on a PC seri
VGA_pll
- 基于FPGA VGA 时钟的设计,关于pll的设计，可以参考一下-The PLL of vga use in FPGA
minus
- 无符号数减法，结果在按下输出键后输出，有清零功能-minus no signal can be clear
DDC
- 数字下变频的FPGA实现方法，十分容易理解，初学者很容易掌握，很好的学习资料-Digital down conversion FPGA implementation method is very easy to understand, beginners can easily master