资源列表
Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex
- 来自于ALTERA官方网站。 本文档详细介绍怎样利用MAX® II CPLD 来实现脉冲宽度调制(PWM)。本设计还利用了MAX II CPLD 的内部用户闪存振荡器，不需要采用专门的外部时钟。 附有verilog源程序。-From ALTERA website. This document details how to use the MAX ® II CPLD to implement pulse width modulation (PWM). This design
ARM_Instruction_Set
- Arm Instruction set document
sy4
- 用VHDL语言设计了一个8位2进制全加器-VHDL language design with an 8-bit binary full adder 2
sy3
- 用两片74194扩展成8位双向移位寄存器-Extended to 8-bit bi-directional shift register with two 74194
dilbalu_fir2
- fpga based fir filtering algorithm
dilbalu_fir6
- digital filter implementation in verilog
dilbalu_fir7
- basic fir filtering in verilog fpga in vhdl
dilbalu_fir8
- finite impulse response filter implementation in verilog
EMV96
- This emv96 kernel code. It is useful for point of sale programmers.-This is emv96 kernel code. It is useful for point of sale programmers.
saa7113
- saa7113的视频采集程序 just test it-saa7113 video capture program just test it
Thermometer
- thermometer vhdl project
AD-PLL
- 基于VHDL的全数字锁相环的设计与实现，quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.