资源列表
vhdl4
- some vhdl sourcecode for freshmen
interlace
- 根据MATLAB中的伪随机交织器产生的交织图案初始化到ROM中，从ROM中读取交织图案对输入数据进行交织。同时也可根据解交织图案进行解交织，同样的算法。-In accordance with MATLAB generated pseudo-random interleaver initialization pattern woven into the ROM, read from the ROM interwoven interwoven pattern of input data. Can a
VerilogHDL
- 不错的Verilog启蒙书 VerilogHDL程序设计与实践-Verilog Primer VerilogHDL good program design and practice
cla16
- 16位超前进位加法器的源代码，整个工程文件都有，是在ISE10.1下建立的，可以帮助理解超前进位原理（对了，是Verilog的，因为上面没看到只好选VHDL了）-16-bit look-ahead adder the source code files have the whole project was established under the ISE10.1 to help understand the lookahead principle (By the way, is the Ver
led_rotate
- 这个是我近期自己在Spartan3E上面写的一个用开发板上的旋钮控制LED灯的流向，可顺时针逆时针，按下旋钮灯灭，开发环境ISE10.1-This is my own Spartan3E write recently, a development board with a knob control the flow of LED lights can be clockwise, counterclockwise, press the knob to the lamp, and the devel
ledwater
- 近期在Spartan3E上写的一个流水灯，从低位到高位的流向，你可以修改代码实现更复杂的功能-Written in recent Spartan3E a water lamp, the flow from low to high, you can modify the code to achieve more complex functions
chipsope
- chipscope的使用教程 适用于初学者-chipscope
jpeg
- jpeg图像处理 用verilog语言处理的源代码-jpeg
XilinxFPGA
- 可以很快学会使用xilinx开发环境ISE，是一个不错的初级入门文件。推荐。-the PDH can easy make u know the sample knowlege on FPGA software ISE.it is worthy reading.
VerilogHDLhuaweirumenjiaochen
- Verilog HDL 华为入门教程.pdf-Verilog HDL
DU
- the DU sample for VHDL coding
config_handbook
- Altera 下的FPGA动态重构的配置方法文档，内有各种Altera下的FPGA芯片连接方式-Altera FPGA dynamic reconfiguration under the configuration document, there are a variety of Altera FPGA chip connections under