资源列表
XillinxFor_CKJH
- 北京百科融创科技有限公司编写的DSP与FPGA接口通信程序源码-Financial Innovation Technology Co., Ltd. Beijing encyclopedia written DSP and FPGA Interface Communication Source
Verilog
- verilog语言入门，详细介绍verilog的用法及基础知识-verilog language entry, detailing the use and basic knowledge of verilog
liuy
- 一个精确时钟的v-log程序，只用一个全局时钟，增加了精确度-An accurate clock in the v-log program, only one global clock, increased accuracy
pci
- 各种码的转换 用于FPJA的编程 挺好用的 有需要的可以-Code conversion for a variety of programming very good use FPJA need to try
93317478verilog.HDL.examples
- FIFO,加法器，乘法器的VERILOG语言-fifo
uart_niosii
- 在nios环境里面写的uart的程序，调试通过，FPGA选用的是EP2C8Q208C.-Nios environment in which to write the uart of the program, debug through, FPGA chosen is EP2C8Q208C.
nios2_multiprocessor_tutorial
- 关于nios里配置多个cpu的方法及其相关的教程-Nios in multiple cpu configuration on the method and its related tutorials
Pingpang
- 乒乓球游戏 基于FPGA 这是一个模拟的游戏-PINGPANG
usb_test1
- usb slaver fifo写程序，将产生的临时数据传送到slaver fifo-usb slaver fifo write programs, will produce temporary data transfer to the slaver fifo
gen_fifo_usb1
- slaver fifo测试模块，分为三个模块，generate产生数据，然后写如fifo.再传如usbslaver fifo-slaver fifo test module consists of three modules, generate production data, and then write as fifo. re-transmission, such as usbslaver fifo
LCD12864IP
- 12864的IP，在艾米电子工作室的nios开发板上可执行-12864 of the IP, in the electronic studio nios Amy executable development board
SampleSPEAKTest
- The document is describing sth