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  1. cpld_ccd

    0下载:
  2. 实现基于CPLD的CCD采集系统设计的VHDL源码,编译通过,-Implementation of the CCD acquisition system based on CPLD design of VHDL source code, compiles,
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:64.84kb
    • 提供者:蹇清平
  1. CORDIC_SINE

    0下载:
  2. 在ISE10.0下的CORDIC算法产生正弦波,可控制其幅度等参数-Under the CORDIC algorithm in the ISE10.0 produce sine wave, its amplitude and other parameters can be controlled
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-18
    • 文件大小:4.78mb
    • 提供者:hushichang
  1. mbtutorial

    0下载:
  2. This tutorial guides you through the process of using Xilinx Embedded Development Kit (EDK) software tools, in which this tutorial will use the Xilinx Platform Studio (XPS) tool to create a simple processor system and the process of adding a cust
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1.38mb
    • 提供者:praveen
  1. modeling_memory

    0下载:
  2. HDL source code for clocking excercise
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:3.71kb
    • 提供者:praveen
  1. clock_divider_lab

    0下载:
  2. Clock divider lab uusing xilinx tools, and simulator like modelsim
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:1.81kb
    • 提供者:praveen
  1. modu

    0下载:
  2. this the verilog code that performs the modulus function ... most importantly it is synthesisable... uses the repeated sub algorithm-this is the verilog code that performs the modulus function ... most importantly it is synthesisable... uses the repe
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:406.19kb
    • 提供者:mma32
  1. nr_divider

    0下载:
  2. This a simple vhdl code that perform division using the non restoring algorithm which is often handy-This is a simple vhdl code that perform division using the non restoring algorithm which is often handy
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:1.06kb
    • 提供者:mma32
  1. PetaLinux_Bootloader_Solutions

    0下载:
  2. A bootloader is required to bring up an FPGA-based Linux system from a power-on or reset. PetaLinux offers a pre-packaged, dual-phase bootloader solution, specially developed and customised for FPGA-based embedded Linux systems.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:82.65kb
    • 提供者:打狗队
  1. TOP_WHIF_CAMRA_240_320

    0下载:
  2. code in vhdl to frame_gerber form camera 320x240 pixle
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:730.33kb
    • 提供者:boazttt
  1. uart232

    0下载:
  2. 基于FPGA的异步串行通行,用MAX232转化的,利用VHDL语言写的,都已调通,有很大的使用价值!-FPGA-based asynchronous serial passage, with MAX232 conversion using VHDL language written in, have been transferred pass, there is a great value!
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-04
    • 文件大小:1.28mb
    • 提供者:xuyanhui
  1. dianziqin

    0下载:
  2. 这个程序是利用Quartus II编写的利用数控分频器设计硬件电子琴,主系统由3个模块组成,顶层设计文件内部有三个功能模块:SPEAKER.VHD 和TONE.VHD和NoteTabs.vhd。模块TONE是音阶发生器,模块SPEAKER中的主要电路是一个数控分频器,NOTETABS模块用于产生节拍控制和音阶选择信号。-This program is the use of Quartus II design prepared by the use of CNC divider hardware
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-23
    • 文件大小:380.08kb
    • 提供者:哈哈
  1. verilog_hdl_code

    0下载:
  2. 适合学习verilog 的初学者,这都是一些简单例子,希望有帮助-Suitable for beginners to learn verilog, these are some simple examples, want to help
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:51.52kb
    • 提供者:liu
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