资源列表
maichong2
- 长度可以控制的脉冲发生器，实际使用过，VHDL编写，放心下载-pulse generator,good choice.
verilog
- 這是一個除法器演算法，是利用移位的方式進行除法運算-This is a divider algorithm is the use of division shift the way
lcm-12832
- 这是基本很完全的功能的显示代码，功能很详细，是一个非常理想的不可多得的源代码。-what is very good
controllable-pulse-generator
- 清华数字集成电路课程，可控脉冲发生器（占空比和周期可调）,仅供新手学习之用-controllable pulse generator
hardware-qpskmodulate1
- 采用硬件描述语言verilog进行QPSK变换的实现的代码- Using hardware descr iption languages Verilog implementation of QPSK converter code
GMSK
- GMSK的FPGA实现程序，全数字GMSK实现方案。-GMSK FPGA-implementation process, all-digital GMSK implementations.
FrqDiv
- VerilogHDL语言编写的分频编序，在FPGA上调试通过-VerilogHDL language compilation of sub-frequency sequence, the FPGA debugging through
AD0809
- verilog实现的“状态机实现AD0809数模转换”。-verilog to achieve a " state machine to achieve AD0809 digital to analog conversion."
waveformgenerator
- The following information has been generated by Exemplar Logic -- and may be freely distributed and modified. -- -- Design name : smart_waveform -- -- Purpose : This design is a smart waveform generator. -The following information has be
ad0809vhdl
- 用vhdl编写的ad0809，不过所实现的不能直接输入模拟信号，而是只能是整数信号-Prepared using vhdl ad0809, but can not be directly implemented by the input analog signal, but can only be an integer signal
tren_de_pulsos
- Generator of pulse train to 50MHz.
vid_clkgen
- Xilinx xapp sink displayport vid clk geneator source