资源列表
error-free
- i want verilogHDL and VHDL source coding.please help me-i want verilogHDL and VHDL source coding.please help me.......
wave
- VHDL 语言 波形发生器（含test beach）。我测试通过-Waveform generator VHDL language (including test beach). I tested by
code
- Design the logic required for a “Dancing Light” system including 5 lights which are turned on repeatedly
13898372spi
- VHDL 实现 spi协议，很实用和通用，希望对你们有帮助哦！：）-VHDL realization of spi agreement, it is practical and versatile, and they hope to help you Oh! :)
digitron_driver_VHD
- 关于easy fpga开发板的led数码管的驱动； --输入：控制端ctrl_digin[2:0]共三位，表示（0~7）控制8个数码管的选通， -- 数据端dig_dtin[3:0]共四位，表示（0~F）控制数码管显示的数字 -- 控制时钟clk_dig一位用于时钟同步 --输出：显示dig_dtout[6:0]共七位，控制A,B,C,D,E,F,G[6:0]小数点不包括在内； -- 控制位ctrl_digout[7:0]共八位，任意时刻只能有一个为高，即只有一个
and2
- and on vhdl code source .
Odd_Fren
- 一个3分频的VHDL程序,方便学习且仅供学习之用-a frequency of three minutes VHDL procedures, facilitate learning and learning purposes only
jianpan
- 这是我用verilog语言编写的矩阵键盘源程序
interface
- 单片机和CPLD的接口实现，能够实现数据的读写。-MCU and CPLD' s interface can read and write data.
rs232_transmit_control
- RS-232 transmir control programmed in VHDL
deserialize-VHDL
- VHDL写的串并转换代码，经ISE13.3测试能用的。-VHDL to write a serial-to-parallel conversion code, can be used the ISE13.3 test.
FIFO
- 利用verilog写的异步FIFO的一种写法-Using a written verilog write asynchronous FIFO