资源列表
FSK_work
- 自己做的基于MATLAB DSP BUILDER的FSK,里面的内容都在，整个工程-MY FSK,have cost much time。please use it carefully。
wallacetree8
- this file is vhdl codes for wallacetree multiplier.it is useful for 8*8 wallacetree multiplier.
uart_tras
- FPGA编写的串口发送程序，调试通过，分模块实现。-FPGA prepared by the serial transmission program, debugging through, sub-modules.
FPGA
- 是fpga的基础入门资料，很好，想学习的同学们可以下下来看看~-Fpga introductory information is the basis of, well, the students want to learn to look down under ~
distrbtdarth
- FIR FILTER DESIGNING USING DISTRIBUTED ARITHMETIC ALGORITHM
yibuqingling
- 含异步清零和同步清零的计数器的设计，内容是源代码，以及相关文件，打开即可-Clear cleared asynchronous and synchronous with the counter design, content source code and related documents, can be opened
ai32-RTL
- verilog code analog output board
VGA_Shell
- this the file that functioning the VGA controller ... and it is workable-this is the file that functioning the VGA controller ... and it is workable..
elc_clock
- verilog实践 elc_clock 电子时钟设计-Verilog design practice elc_clock electronic clock
Introduction-_FPGA_mid3
- fpga的中级教程，中级3_数字电路提高，请认真学习-fpga intermediate tutorial, intermediate 3_ improve digital circuits, carefully study
seg
- 用VHDL编写的数码管显示程序（数码管共用数据线），带有进制转换功能-Written in VHDL, digital tube display program (digital control shared data line), with a binary conversion
exp15
- 本实验的任务就是设计一个秒表，由于计时时钟信号为50MHz，因此需要对系统时钟进行500000分频才能得到。另外为了控制方便，需要一个复位按键、启动计时按键和停止计时按键，分别选用实验箱按键模块的KEY0、KEY1和 KEY2，按下KEY0，系统复位，所有寄存器全部清零；按下KEY2，秒表启动计时；按下KEY1，秒表停止计时，并且七段码管显示当前计时时间，如果再次按下KEY2，秒表继续计时，除非按下KEY0，系统才能复位，显示全部为0000－－00。-The task of this exper