资源列表
UART
- A sample that describe how to make wiring between modules using verilog ,it contain two stages of inverter of SW1 as input and LD7 as output
AM_CORDIC
- 基于CODIC算法的通用调试模块，编译通过-Common debugging module based on CODIC algorithms, compiled by
daling
- 利用MUXPLUSII平台实现工业打铃功能。-MUXPLUSII platform using industry fight bell function.
S9_PS2_LCD
- 键盘输入液晶模块显示字符,在液晶显示屏上显示从PS2键盘输入的字符-Keyboard input LCD display module characters displayed in the LCD screen from the PS2 keyboard input characters
vhdlexplication
- vhdl tutoriel that explicate how to use it
clock
- 基于VHDL的数字时钟的设计，能直接在开发板上看到运行结果-VHDL-based design of the digital clock can be seen directly in the development of on-board results
important
- importatn document for fir filter implementation by distributed arithmetic
add_gen
- 地址产生器,其采16*15矩阵,行输入,列输出-Address generator, the adoption of 16* 15 matrix, line input, line output
lab_3
- full adder 32 bit one you
LCD12864
- LCD12864汉字显示，用VHDL工程的12864显示屏汉字显示-LCD12864 character display, works with VHDL 12864 Chinese character display screen
L-CBF
- verilog code for lcbf
FPGAadder
- 现场可编程门阵列（FPGA）是目前应用非常广泛的一种专用集成电路。在FPGA平台上实现了2位全加器硬宏的设计-Field programmable gate array (FPGA) is widely used as a specific integrated circuit. The FPGA platform for a two full adder hard macro design