资源列表
VHDL-Finished-Homework
- 有闹钟功能，可以定时的电子时钟，还可以设定定时时间-Have alarm clock function, the electronic clock timer, you can also set the regular time
H891
- 基于ALTERA的NIOS系统的车载显示系统(车载摄像头和TFT显示器)设计源代码-Car ALTERA NIOS system based display system (car camera and TFT display) design source code
Verilog-HDL
- 《Verilog-HDL实践与应用系统设计》一书中的光盘源文件- Verilog-HDL practice and application of system design, a book on CD-ROM source file
uart
- vhdl编写，完成了uart的接口设计，包括信号检测，判决等-vhdl prepared to complete the uart interface design, including signal detection, decision, etc.
ALU
- ALU CPU内部运算器 这个是ALU内部个模块的VHDL程序和原理图-ALU THE ONE PART OF CPU .ZHIS PART INCLUDE VHDL
LabALU
- vhdl编写的8-bits ALU,包括加减法与或非6种工作模式-vhdl write 8-bits ALU, including the addition and subtraction and non-operating mode 6
wave_gen
- 波形发生器，可以产生正弦波，锯齿波，方波。Verilog语言编写-Waveform generator, can generate sine wave, sawtooth wave, square wave. Verilog language
13
- 风险成因何在?银行财会如何专业防范风险?-What causes the risk? Bank accounting to professional risk prevention?
shuziCLOCK
- 基于FPGA的数字钟程序，结构思路清晰，适合初学者-the clock for FPGA
inout_test
- there are two madules,both of them contain an inout port,As module1 sends out data on its inout port,the inout port on second module would be an input,and vice versa
hdl-2015_r2.tar
- AD9361 IP核，Linux版本，Vivado2015.2(AD9361 IP core, used on Linux, Vivado2015.2)
PipelineCPU2
- Modulsim下Verilog写的五级流水线32位简易CPU-five level pipeline CPU written in Verilog.