资源列表
decoder
- VHDL decoder. For converting binary to seven segment,
the-design-of-states-machine
- 状态的设计教程，主要介绍了复杂时序电路的设计方式！-the design of states machine
CPLD
- 基于CPLD 的交通灯设计
edc_spi_command
- 单片机和FPGA的通信程序，发送5个数，传输稳定，可以自行修改可一次传多个数-MCU and FPGA communication program, send five the number of stable transmission, you can modify the number may be more than one pass
mydds1
- Write your own DDS generators, square wave, triangle wave, sine wave, you can also enter any Waveform files
sopc_altera_monitor_program
- This book descripe sample example to use altera monitor wih quartes
AD9708
- AD9708是高速AD转换芯片，采用VHDL实现10MSPS高速AD数据采集-AD9708 is high speed a/d conversion chip,10MSPS,using VHDL
vga_test
- 用黑金板AX309实现对VGA口的控制，驱动显示器显示。程序基于ISE14.7，语言为Verilog。实测可用。(The black gold board AX309 realizes the control of the VGA port and drives the display of the display. The program is based on ISE14.7 and the language is Verilog. Measured available.)
random_num
- Random number generation
MY_DCM
- DCM测试模块，带有仿真文件和仿真结果，对于初学者有一定的参考价值-DCM test module, and simulation results with the simulation files for beginners have some reference value
QUARTUSIICONFIGURE
- 这是一个有关FPGA外部配置的一个视频教程，希望大家下载。-This is an external FPGA configuration a video tutorial, I hope you download.
SZZ
- 这是一个数字钟的VHDL语言，具有调时、调秒、调分功能，同时，还具有十二小时制向二十四小时制切换功能-This is a digital clock in VHDL language, with a tune, the tone seconds and sub-transfer function, while the system also has 12 hours to 24 hours the system switching function