资源列表
veriloghdl-tutorial-135-cases
- veriloghdl教程135例，包含很多基础代码，可以用于学习，或者扩展为其他应用-veriloghdl tutorial 135 cases, including a lot of infrastructure code that can be used to study, or extended to other applications
ISE9.1user_guide
- ISE9.1 user guide ISE开发环境使用指南-ISE9.1 user guide
arlut_fifo_interface
- fifo控制器，可以加到nios系统下，通过nios进行FIFO的读写，经过本人的项目验证-fifo controller, can be added to the nios system, through the nios to FIFO read and write, after I verified the project
counter
- 此代码是一个小的计数器，主要驱动FPGA开发板上的LED灯的亮灭。-This code is a small counter, the main driver FPGA development board bright LED lights eliminate.
Desktop
- 四选一多路选择器 modelsim testbench-Select more than one four-way selector modelsim testbench
clock
- 电子闹钟，实现了基本的计时功能，此外还能设定闹表时间。-Electronic alarm clock to achieve the basic timing functions, in addition to also set the alarm clock time.
shifter
- 8位移位器，实现算术左、右移位，逻辑左右移位和循环左右移位。-8-bit shift device to achieve arithmetic left and right shift, logical shift left shift and cycle around.
mina
- 四位密码锁，默认密码3456，三次错误输入后上锁。-4 locks, the default password 3456, entered incorrectly three times after the lock.
e2prwctrl
- EEPROM芯片读写控制器的VHDL语音程序设计-EEPROM chip to read and write controller VHDL Voice program design
ledclock
- LED电子时钟控制器的VHDL语言程序设计-LED electronic clock controller VHDL Language Program Design
led7drv
- 7段LED驱动器的VHDL语言程序设计源码-7 segment LED driver source VHDL Language Program Design
ddr_verilog_xilinx
- xilinx公司原版的DDR时序控制源码.-xilinx' s original source code of the DDR timing control.