资源列表
Old_CPLD_prj
- simple altera pld example
dCACHE
- Vhdl写的数据cache,根据Verilog程序改编-Vhdl write data cache
51
- 可以在短时间内对你熟悉51的结构，起很大的指导作用，可以综合通过的。-In a short time you are familiar with the structure of 51, played a great guide can be integrated to pass.
s3esk_startup
- 利用kcpsm3控制lcd显示 平台：ise 10.1， picoblaze， Spartan3e 开发板 说明：综合按键和lcd、led的功能，思想简单，需要新技术，适合想在fpga方面深造的人。-using kcpsm3 for lcd display platform: ise 10.1， picoblaze， Spartan-3E FPGA Starter Kit Board comment: involve lcd/led/switch, simple mind bu
tutorial
- 计数器 平台：Xilinx ise 10.1 说明：和ise10.1快速帮助手册配套的源码，适用于初学者。-counter platform: Xilinx ise 10.1 comment: supplement to ise quick start tutorial 10.1, suitable for freshman to fpga and ise software.
e7v4
- 数字钟：显示，设置时间，设置闹铃（报时），秒表。 平台：quartusII 5.1。 说明：此版本中已将系统时钟调快，自己稍微改动一下即可，小小的考验，做出来会更有成就感！-digital clock：display time, set time, set alarm(use speaker to alarm), stopwatch. platform: quartusII 5.1 comment: there s a place to change if you want th
DesignrecepiesforFPGAs
- This book provides a rich toolbox of design techniques and templates to solve practical, everyday problems using FPGAs. Using a modular structure, the book gives easy-to-find design techniques and templates at all levels. together with functional cod
VHDL2008JusttheNewStuff
- VHDL2008 Just the New Stuff, as its title says, introduces the new features added to the latest revision of the IEEE standard for the VHDL hardware descr iption language. Written by the Chair and Technical Editor of the IEEE working group, the book i
TheDesignersGuidetoVHDLVolume3
- VHDL, the IEEE standard hardware descr iption language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. Th
Leds
- Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
daima
- 关于《无线通信FPGA设计》的源代码，有matlab和fpga的实现，非常好，特别是对于做信号处理的。-On " Wireless Communications FPGA design" of the source code, there is matlab and fpga implementation, very good, especially for doing signal processing.
UARTipcore
- 这是一个关于UART的IP核，用VHDL写的。经过本人的鉴证，非常实用并且写的非常好。-This is one of the IP core on the UART, using VHDL written. After my verification, very practical and very well written.