资源列表
mul
- 八位乘法器的VHDL程序，按照乘法的运算规则利用分支语句判断所有情况，最后累加求的结果-8 multiplier VHDL programs, in accordance with rules of multiplication operations to determine all the circumstances of the use of a branch statement, the final cumulative result of demand
VHDLseven-segmentdecoder
- VHDL在液晶显示上的七段译码器源码,应用于FPGA,ASIC等硬件设计-VHDL in the seven-segment liquid crystal display on the decoder source code, used in FPGA, ASIC and other hardware design
segment
- 设计一个运算器，可实现输入的2个一位十进制数的加、减运算。要求：输入提供十个数字键，先转化为8421码，再运算，输入的数据和输出结果都要以七段显示译码器显示出来（仿真波形）。输入模块、运算模块、数据转换模块要求用不同的模块分别实现。小孟浩搜索不到吧-Design a calculator, can be one of the input of two decimal addition, subtraction operations. Requirements: Enter the ten num
Digital_Filter_FPGA
- Digital Filter in VHDL
testbench
- testbench for Carry look ahead adder
VHDLnf
- VHDL实现任意整数分频，--只要把n设置成你要分频的数值就可以了-VHDL arbitrary integer frequency, -- n as long as you want to set the frequency of the numerical breakdown on the
div3
- 用VHDL硬件描述语言实现的良好运行的三分频电路
second
- 一个简单的用vhdl写的计秒功能的小程序.
div
- 二进制除法器，采用移位相减的方法实现，位数可调-The source code of a divider
UART
- UART发送数据 中断接受数据 UART发送数据 中断接受数据-UART interrupt receive UART transmit data
booth.vhd
- this the source code for booth s multiplier. used to low power dsp architecture.-this is the source code for booth s multiplier. used to low power dsp architecture.
fsm
- 三段式状态机的典型写法，verilog实现-The three section type of typical state machine method, Verilog implementation