资源列表
ASCII_PACKAGE
- ASCI package in VHDL for verilog implementation
uarttx
- fpga板 verilog写的串口发送数据的模块，主要可以看下思路，也是可用的-Fpga board verilog write serial port to send data module, the main can look at ideas, is also available
dffwewe
- 自己刚编写的vhdl语言来实现的D触发器，自我感觉还可以，也通过了编译，如果有需要就下载去看看吧-just prepared their own language to achieve vhdl D flip-flop, but also a sense of self, but also through a compiler, If there is a need to look at the downloaded Look here
hello_flash
- hello_flash是ALTERA的NIOSII核的标准程序。读写FPGA外带的Flash。-ALTERA the hello_flash is standard procedure for nuclear NIOSII. Hit-and-run of the FPGA to read and write Flash.
20096411m5349886
- 本程序实现任意占空比产生，已经在easyfpga030综合过-This procedure generated to achieve an arbitrary duty cycle
SN65HVS882
- core to read digital inputs of SN65HVS882-core to read digital inputs of SN65HVS882
m16c-flash.tar
- M16C Flash reader/writer using python. Allows to read/write M16C flash from arbitrary addre-M16C Flash reader/writer using python. Allows to read/write M16C flash from arbitrary address
Fifo_lk
- 简单好用的Fifo 128x32 Verilog-Fifo 128x32 Verilog
key_state
- 这是用vhdl编写的状态机来实现对灯的控制。比较简单，但对于状态机的理解是更进一步。-It is written vhdl state machine to achieve control of the lamp. Is relatively simple, but for the state machine is further understood.
VHDL基于实验开发板的按键处理与LED显示
- VHDL基于实验开发板的按键处理与LED显示。
cnt
- 俩个比较好的计数器的vhdl代码：一个是n位通用计数器，一个是的用到的语法比较全面。是比较好的学习资料-Both a relatively good counter VHDL code: one is the generic n-bit counter, one is the syntax used in the more comprehensive. Is a better learning materials
uart_transmitter
- This UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.-This is UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.