资源列表
SIN_NEW1Hz
- 正弦波信号的产生,频率为1Hz,FPGA处理模块各部分所需工作时钟信号由输入系统时钟信号经分频得到，系统时钟输入端应满足输入脉冲信号的要求-generte sin wave, the frequence is 1Hz,FPGA processing module is required to work various parts of the system clock signal from the input clock signal by dividing the system clock
digital-clock
- digital clock by verilog
20100413160457488989
- eda 开发系统相关软硬件介绍KX_7C5E+型EDA开发系统配置及实验简介-sf
FPGA_LCD_BEST
- FPGA液晶驱动程序，调试通过，可以直接在硬件上跑-This code is directly through debugging in hardware to run
jiyuVHDLshizhongchengxu
- 基于VHDL的时钟、正弦波和方波实验报告-VHDL-based clock, sine and square wave experiment report
paobiao
- 简单跑表的设计与实现,包含时钟的分频模块，及60进位和十进位模块，可以实现跑表的基本功能！-a design for a stopwatch,
PS2
- PS2鼠标键盘协议 PDF 和相关程序-PS2 mouse and keyboard protocol PDF and related procedures
dianzibiao
- 这个是我刚刚用过的程序，只要硬件电路正确，绝对没问题-This is the procedure I have just used, as long as the hardware is correct, absolutely no problem
xlx_s3a_evl-sch
- Xilinx SP3 开发板电路原理图，是学FPGA设计和电路设计的参考资料。-Xilinx SP3 development board circuit diagram, is to learn FPGA design and circuit design reference.
Modelsimstudying
- 看一下教程对学习modelsim的使用很有帮助-Look at the tutorial very helpful in learning the use of modelsim
ad
- 基于fpga的ad转换实验，本人已经测试，绝对真实，erilog语言-ad zhuanhuan