资源列表
code
- 5分频器的源代码编写过程中建议大家先画图，在用代码描写，清楚明了-5divider code， and easy to understand,you will find it is easy to write
HDLSample
- FPGA的周边电路的设计源码用HDL语言编写-Peripheral circuit design FPGA using HDL language source
v
- verilog code for a synthesizer based on Terasic s Multimedia development board. (MTDB) and Altera FPGA.
e1framerdeframer_latest
- 实现E1信号的成帧、CRC校验功能，双向通信，双工工作，实际检验通过-E1 signal to achieve a framing, CRC checking function, two-way communication, duplex work, the actual test by
MEdia_control_i2c
- 将来自MAC的GMII8B码进行8B/10B编码。FPGA输出10路10B码的数据，如有必要，可配置*SDRAM，FPGA还得实现SDRAM控制器，-Will come from the MAC' s GMII8B codes 8B/10B encoding. FPGA output 10 Road 10B code data, if necessary, can be configured to plug SDRAM, FPGA have to realize SDRAM contro
single_port_ram
- Single port RAM file VHDL source code
The.design.of.the.voting.machine
- 表决器的设计 设计一个三人的表决器，其中有二人以上同意则投票通过。演示结合实验箱上A区、J区的LED及按键。工作过程如下：带锁的按键按下时，按键上的灯亮表示投票同意；按键松开时，灯熄灭表示投票反对；SW1-SW3这三个按键是3人的投票键，L1灯亮表示投票通过，且蜂鸣器响；L1灯熄灭表示投票未通过，且蜂鸣器不响。利用原理图和VHDL编程相结合的方法来实现-The design of the voting machine
loveyou
- Verilog实现love you 状态机的小例子-a small example of the realization of the love you state machine with Verilog
Source
- source for your o2 xda atom
jiaotongdeng-
- 可以实现，交通灯的模拟，自己设定中间时段长短-Can be achieved, the simulation of traffic lights, the middle of their set length of time
Three-voting-machine
- 三位表决器，源代码-Three voting machine
hanzi-xianshi
- 这是一个测试的汉字显示源代码程序，可以测试led显示-This is a test of the Chinese characters display the source code program, you can test led display