资源列表
FFT
- 基于FPGA的1024点fft实现VEILOG-1024 point fft based fpga
fpga
- 利用超高速硬件描述语言(VHDL)在现场可编程逻辑门阵列(FPGA)上编程实现的纯数字式等精度频率计，不但具有较高的测量精度，而且其测量精度不会随着被测信号频率的降低而下降。为了实现对任意信号进行频率测量，在前端输入加整形电路即可。-The cymoneter that be implemented with using the VHDL (Very High Speed Integrated Hardware Descr iption Language) to program into the
LCD_test
- (1)verilog Hdl语言学习。（2）1602LCD的verilog程序。-(1) verilog Hdl language learning. (2) 1602LCD the verilog program.
traffic_controller
- it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.-it is a verilog code written for traffic light controlle
traffic_ligt_controller_veeren
- traffic light controller
game_timing
- 比赛计时 棋类比赛 包括篮球 羽毛球 乒乓球 -time couting
ourdev_481478
- FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第二个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The second document
fft_1024
- 基于FPGA的1024点的verilog和VHDL实现-Based on FPGA 1024 verilog and VHDL implementation
TLC5510
- tlc5510的vhdl程序，有详细的工程文件，为初学者提供很好多的资料-tlc5510 of vhdl procedures, detailed engineering documents, in order to provide a good amount of information for beginners
e1framerdeframer
- E1成帧器和解帧器的FPGA实现源码，测试可用-E1 Framer deframer
count10
- 10进制计数器,用于一般的计数、计时等基本元件。-ten counter
multiply
- 实验报告中完成以下功能：在maxplus2 环境下，完成4bit × 4bit 运算功能，并模拟显示出相关内容，设计动态扫描显示电路，显示两位字符，以便用在4bit × 4bit运算中。 （附源程序代码）-multiplay under maxplus2，use VHDL