资源列表
can_rtl_verilog.tar
- can控制器的verilog语言实现 （还要更多的说明语言了吗？我不知道该写什么了）
SPI接口音频Codec实验
- ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
example5
- 按键控制：8个按键对应8个数字显示，初始值为0。-Key Control: 8 buttons corresponding to 8 digits display, the initial value is 0.
DE2_i2sound
- 基于FPGA的音频信号A/D转换，适用于DE2开发板。-FPGA-based audio signal A/D conversion, for DE2 development board.
logicfunction
- a simple VHDL architecture for logic function-a simple VHDL architecture for logic function
FPGA-pin-assignment
- FPGA管脚分配需要考虑的因素，经验之谈，有很强实用价值-it is about The FPGA pin assignment
Project10
- Hamming codes can detect up to two-bit errors or correct one-bit errors without detection of uncorrected errors. By contrast, the simple parity code cannot correct errors, and can detect only an odd number of bits in error. Hamming codes are perfect
8051source_2_8
- 这是兼容的8051 VHDL CPU实现，应该不算侵权吧。 上帝保佑！-This is compatible CPU 8051 VHDL, it is not a tort. God bless!
eda6
- 以Altera公司的MAX+plus II为工具软件，采用Verilog HDL文本输入设计法设计8位二进制加减计数器，生成元件符号-Altera s MAX+plus II tools software, using Verilog HDL text input method to design8 binary addition and subtraction counter, generating element symbol
FORM_FRONT
- 设置窗体的属性，使当前窗体保持在弹出窗体的前面。-Set the form' s properties so that the current form is maintained at the front of the pop-up window.
voter
- 少数服从多数表决器，Verilog HDL语言描述，包含文件说明和波形截图-Majority voter, Verilog HDL language descr iption, contains the file descr iption and waveform capture
Assignment-2.1.tar
- verilog codes for different basic digital circuits elements new