资源列表
EDA
- 移位相加8位硬件乘法器电路设计,该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。-Add 8-bit hardware multiplier shift circuit design, the multiplier is composed of 8-bit adder to temporal order, 8-bit multiplier design.
SRAM@DMA实验
- ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
clock
- 数字电子时钟 的 VHDL 状态机程序 -VHDL procedures for electronic clock
JTAG_timing
- 用VHDL实现的JTAG时序，其中有16个状态机来控制产生该时序。-jtag timing implemented by VHDL
LAB2_7ENT1003
- This is basic of vhdl
lab2
- This is basic of vhdl
Q8051
- A 1T51 core which contain 16 verilog files. this mcu core consiste with standard 51
csa_verilog_rtl
- CSA加扰算法verilog实现，代码经过fpga验证，可以正确实现该算法。-CSA verilog rtl codeing
step_1
- fpga的数码管显示程序，可以让你快速入门，里面有参考程序-fpga digital tube display program that allows you to get started quickly, there are reference program
KB
- 矩阵键盘的扫描程序，利用状态机思想进行编程，编程环境keil-Matrix keyboard scanner, using a state machine programming ideas, programming environment keil
Nithyanan-prog
- Evolve a Combinational Circuit on a FPGA Chip
coding-for-Simulation
- For filter --a novel area efficient architecture in verilog and testbench is developed