资源列表
dwt2d_latest[1].tar
- 小波变换的开源代码（Verilog HDL）包括有测试文件，本人看过，挺好。-code of dwt
a11
- I2C控制器的Verilog源程序 -I2C controller Verilog source code
ug_rs-compiler
- altera RS编译码器datasheet-the datasheet of the rs encoder and decoder of altera
Spartan3E.rar
- Spartan3E的LCD字符滚动显示源程序，具体内容见注释,Scroll Spartan3E character LCD display the source code, see the specific contents of the Notes
06219426Spartan3E
- VHDL汇编语言原理及源代码。spartan 3e开发板试用。-VHDL language.
answer
- 通过用verilog语言编写一个简单的数字系统，实现经典猜谜游戏的功能。-Verilog language by using a simple digital system, to achieve the classic guessing game of functions.
定点乘法器设计
- 讲解FPGA逻辑设计的乘法器设计方法，优化逻辑资源(Explain the multiplier design method of FPGA logic design and optimize logic resource)
RISC-CPU-design
- 16位RISC-CPU设计，高四位为操作码，低12位为地址，寻址空间位4KB。包含12条指令（预设16条指令），3个基本测试文件及其Modelsim仿真结果。-16-bit RISC-CPU design, the high four bits for the opcode, the lower 12 address, the address space of 4KB. Consists of 12 instructions (default 16 instructions), the thre
uart_rx_tx
- 基于sp605开发板的一个串口收发程序。包含了所有ise产生的完整的文件（ucf等），通过串口调试助手测试通过。共有四个模块构成。-Program based on the the sp605 development board serial transceiver. Contains all ise complete file (ucf etc.), by serial debugging aides tests. A total of four modules.
5421bcd
- 5421bcd vhdl-5421bcd vhdl
filter-design
- MBD-FPGA数字滤波器设计基本流程,基于DSP builder-MBD-FPGA basic process of digital filter design
moshijishu
- FPGA基础代码，模10计数器，可实现加计数-FPGA code base mold 10 counters, counting can be achieved