资源列表
RS232_RECIBE
- Receive from Hyperterminal RS232 to Spartan 3E
verilog_sw_led
- 采用verilog编写的FPGA程序，程序的功能是按键按键消抖，quartus II 开发。芯片型号是EP2C35F484C7，时钟50MHz。-FPGA verilog to write the program, the program function is the key button is debounced, quartus II development. The chip model is EP2C35F484C7, clock 50MHz
qdr2_top
- xinlinx QDR2 contoller for verilog
vgachar
- verilog实现的VGA控制器,简易VGA控制器-verilog achieve VGA control
ps2_fpga
- 键盘输入，在数码管显示对应按键的编码，从中了解键盘输入原理-Keyboard input, the digital display corresponds to the encoding keys
dvd-aca-project-files
- It is a files that contain source code for fetch and decode unit in verilog
VHDL
- 表决器 奇校验器 3位比较器 4选1 数据选择器-The odd parity voting 3 comparator election of a data selector
DE2_i2sound
- DE2_i2sound.rar
THDLPP
- THDL++ Tutorial. THDL++ is a HDL
CPLD_TEST
- LED显示屏动态显示的测试程序，驱动用2个74LS138构成4-16译码器，采用1/16扫描方式。-LED display shows the dynamic test procedure, the driver constitute 4-16 with two 74LS138 decoder, the 1/16 scan mode.
Development-of-Web-Based-Educational-Modules-etd.
- Design of Optimized Reversible BCD Adder-Subtractor 229
lecture11
- verilog for counting use 7 segments-verilog for cycle show in pic