资源列表
project4
- 设计一个14阶FIR滤波器，已给出滤波器系数以及验证程序-A 14-stage FIR filter design, has given the filter coefficients and the validation process
exer4
- 设计可以对两个运动员赛跑计时的秒表，verilog的大作业 -Design of the two athletes running the stopwatch timing, verilog great job
exer2
- 给定一个频率为33MHz的时钟，试利用该时钟得到一个基本均匀的2.048MHz时钟-Given a frequency of 33MHz clock, try to use the clock to get a basic uniform of the 2.048MHz clock
exer1
- verilog的大作业题，用Verilog描述一个遥控器，仿真并综合出电路图-verilog big job title, descr iption of a remote control with Verilog simulation and synthesis of the circuit
wcy
- FPGA-based direct digital synthesizer (DDS) design (source code)
Thyristor_gate_control_pulse_generator
- 一个例子 VHDL代码设计时，它是控制一个例子 晶闸管。-An example VHDL code designs are presented,it is for controlling an example thyristor.
VHDL_code_for_DAC_controller
- 一个VHDL代码设计时，它是控制 在AD7524数字至模拟转换器-An VHDL code designs are presented ,it is for controlling the AD7524 digital-to-analogue converter
ditong
- 低通滤波器ewb设计图，低通滤波器ewb设计图-Ewb design low-pass filter, low pass filter ewb design
jtd
- 交通灯 ADADDF VHDL-TRIFFIC LIGHT VHDL
yejing1602
- fpga完成液晶模块的测试功能，效果良好 ，先是清楚-fpga finished LCD module test functions, good effect, first clear
zlg_avalon_ps2keyboard
- fpga主要完成键盘的测试功能，非常完美，实现效果良好-fpga main function of the completion of the test keyboard, perfect to achieve good results