资源列表
chap6
- Verilog135例，chap3-chap12,初学必备-Verilog135 cases, chap3-chap12, beginner necessary
chap5
- Verilog135例，chap3-chap12,初学必备-Verilog135 cases, chap3-chap12, beginner necessary
chap3
- Verilog源代码一共135例chap3-chap12，初学必备-Verilog source code for a total of 135 cases of chap3-chap12, beginner necessary
VerilogXiaYuwenExample
- Verilog数字系统设计教程（夏宇闻著） 例题源程序-Verilog Digital System Design Tutorial (Xia Yu smell) Example source code
VHDL_ip
- 基于VHDL语言的可移植通用存储器IP核的实现，本文介绍了一种利用VHDL 硬件描述语言实现可移植通用存储器IP 核的思路与方法，实验研究表明，该方法具有可移植性强、扩展性及灵活性好的特点，有效地改善了数字系统设计的效率。-VHDL language based on universal portable memory IP core implementation, this paper presents a VHDL hardware descr iption language using a
paper_FPGA
- 基于FPGA控制的高速固态存储器设计，对固态存储器进行了需求分析, 根据航天工程对高速固态存储器的需求, 确定了设计方案。 针对航天工程对高速固态存储器速率要求较高的特点, 在逻辑设计方面采用流水线技术、并行总线技术。在器件选择方面, 采用LVDS构成接口电路, FPGA构成控制逻辑电路电路, SDRAM芯片阵列构成存储电路。设计了高速固态存储器。该设计简化了硬件电路, 大大提高了存储数据的速率。-FPGA-based control design of high speed solid s
verilog_program
- 各种初学Verilog者需要练习的实例代码集锦，包含加法器，BCD计数器，2分频，交通灯等等！-Beginners need to practice a variety of examples of Verilog code highlights, including the adder, BCD counters, 2 frequency, traffic lights and more!
the_common_module_in_EDA
- EDA实验中用到的常用模块程序，内容丰富，下载绝不后悔！-EDA experimental procedures used in common module, content rich, download no regret!
Verilog_examples
- 强大丰富的Verilog实例资料，内含大量简单实用的Verilog源代码，带你快速入门！-Verilog examples of powerful data-rich, containing a large number of simple and practical Verilog source code with you a quick start!
synplify_makefile
- synplify、ise和verdi在linux上的makefile；多个工具集成在一个文件管理，方便快捷，值得参考-the makefile for synplify, ise and verdi on Linux multiple tools integrated into a document management, convenient and valuable reference! ! !
DE2_70_CAMERA_V1.0.3
- terasic 5mp camera also quartus 9.1 support
cronometru
- crono made on fpga on vhdl code ,