资源列表
yinbo
- 密码锁，输入正确的密码门开，错误的密码灯亮，连续输入三次错误的密码，发出报警声，直到输入正确的密码-Password lock, enter the correct password the door opened the wrong password lights, continuous input an incorrect password three times, alarm sound, until you enter the correct password
BIN_CV_MEN
- 可將2進位檔案 轉換成適合verilog應用的文字檔-2 into digital files can be converted to a text file for verilog applications
M-sequence-generator
- M sequence generator using VHDL-M sequence generator
fifo2
- FPGA的异步先入先出程序，VHDL的fifo-VHDL and fifo
ADS7852
- FPGA采用VHDL语言驱动ADS7852的程序,-FPGA and ADS7852
book
- 一本VHDL的好书，里面介绍了如何利用VHDL做数电实验！-A VHDL good book, which describes how to use VHDL to do the number of electrical experiments!
quartusII8.0_crack
- quartusII8.0软件的使用许可，需要学习的朋友可以拿来使用，不要外传，-quartusII8.0 software use license, you must learn from a friend can put to use, not rumor, thank you
10_100m_ethernet-fifo_convertor_latest.tar
- 10_100m_ethernet-fifo_convertor_latest,使用verilog语言写的，请需要的下来参考，不要用于商业，谢谢！-10_100m_ethernet-fifo_convertor_latest, using the verilog language to write, please refer to the needs of down and not used for commercial, thank you!
verilogHDL
- 用Verilog HDL语言实现通用异步收发URAT装置-With the Verilog HDL language to achieve universal asynchronous receiver URAT Device
encode
- 实现轴编码器的程序，对控制是比较有用的哦-Shaft encoder to achieve the procedure, control is more useful oh
motor3_and_motor4
- 程序是CPLD双计数器的程序，主要用于电机编码器计数-Program is CPLD pairs of counter procedures, mainly for motor encoder counts
VHDL_codes
- include VHDL code -include VHDL code