资源列表
use_SRAM_design_FIFO.pdf
- 利用sram技术设计的一个FIFO-failed to translate
vhdl_zhiliudianjikongzhiqi
- 用vhdl编写的一个直流电机控制器-Vhdl prepared using a DC motor controller
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
fifo_memory
- 用vhdl设计的一个FIFO存储器-Vhdl design with a FIFO memory
a_good_game
- 用vhdl语言编写的一个小的游戏-Vhdl prepared with a small game
chinese_correct
- 一个关于汉字纠错码器的vhdl设计-It' s error-correcting character design vhdl
vhdl_bujindianjikongzhiqi
- vhdl编写步进电机控制器（基于FPGA）-the preparation of vhdl stepper motor controller
shuoming
- VHDL 开发一个七段数码管显示时钟,非常不错,欢迎分享下载.-VHDL IS VERY EASY.WELCOME LOAD
VGA
- 该项目在VGA显示器上显示8色竖彩条,使用的是verilog HDL语言编写，言简意赅，一目了然-VGA display of the item shown in the 8-color vertical color
fifo_ptrs_gray
- fifo pointers in verilog gray code utilization for synchronius
DE2_LCM_CCD
- DE2 CCD数码相机源代码，下载即可使用。方便学习。-DE2 CCD digital camera source code, you can use to download. Facilitate learning.
Verilog_tutorial
- Verilog_tutorial联系指导 Verilog_tutorial联系指导-Contact Verilog_tutorial contact Verilog_tutorial guidance guidance guidance Verilog_tutorial Contact