资源列表
Limi
- 用VHDL设计一个6位二进制计数器：用VHDL设计一个6位二进制计数器-VHDL design with a 6-bit binary counter
ledall
- 实现了LED点阵上的汉字的动态显示设计,通过修改rom模块能够改变所显示的汉字-To achieve the dynamic LED dot matrix Chinese characters display design, by modifying the ROM module to change the display of Chinese characters
Adaptive-filter
- 一种LMS数字自适应滤波器的硬件设计与应用-Adaptive filter
PWM
- FPGA硬件设计，完成PWM脉宽调制电路的硬件描述语言设计。能够运行成功。-FPGA hardware design
MyFCS1
- FPGA软硬件，完成飞行控制系统任务，包括数据通信、飞行控制律解算等。-FPGA software and hardware
UART interface
- UART11k Universal Asinchs Reciver Transmiter
USB VHDL
- Full USB interface fo FPGA CPLD VHDL
i2s interface
- i2s interface VHDL language FPGA. Using for MEMS microfone
demodulation
- QPSK解调程序，verilog语言，基于FPGA的硬件描述语言-QPSK demodulation
IIC_verilog
- IIC控制器，源代码verilog,WISHBONE总线-IIC controllers, the source code verilog
hdbn
- This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703. Note: HDB2 and
FFT_VHDl
- VHDL实现快速傅里叶变换，内附带资料以及源代码。-VHDL fast Fourier transform, within the supplied data and source code.