搜索资源列表
mulf2m.rar
- 椭圆曲线加密算法中的乘法器的生成，主要功能是实现在素域上的多项式模P(大素数）乘的运算。,Elliptic curve encryption algorithm to generate the multiplier, the main function is to achieve in the Su-domain polynomial module P (large prime numbers) by the operator.
multiply2.rar
- 18bit的booth乘法器 采用booth2编码 Wallace压缩树 以及超前进位结合进位选择的36bit高性能加法器,18bit multipliers used booth2 the booth encoding and Wallace tree compression-ahead into the location choice of high-performance 36bit adder
cf.rar
- 乘法器功能 直接实现两个数字信号的相乘～,Multiplier features two digital signal direct implementation of the multiplication ~
cheng1.rar
- 用VHDL实现十六位移位乘法器 才有移位相加法来实现,Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
RTL
- 256位有符号整数乘法器，个人学习时编写，接口为IPBUS，用verilog语言编写-256-bit signed integer multiplier, when writing individual learning, the interface IPBUS, with verilog language
MULTI8X8
- 乘法器的硬件快速实现，采用Vhdl语言，对于学习芯片开发的人有用。-multiply is completed by vhdl.
Adaptive-digital-filter
- 自适应数字滤波器中乘法器的硬件设计，用VHDL语言实现自适应数字滤波器。-Adaptive digital filter in multiplier hardware design, using VHDL language adaptive digital filter.
multi8x8
- 该源码为8位乘法器的VHDL语言描述，由一个8位右移寄存器，2个4位加法器例化成8位加法器，一个16位数据锁存器构成。采用移位相加的方式，从被乘数的低位开始，与乘数的每个位移位相加求和。最后实现其乘法器功能。-The source code for the 8-bit multiplier in VHDL language to describe, from an 8-bit right shift register, two 4-bit adder example into 8-bit add
MSP430
- MSP430头文件详解，介绍特殊功能寄存器地址和控制位，看门狗定时器的寄存器定义， 硬件乘法器的寄存器定义。-Detailed MSP430 header files, describes the special function registers the address and control bits, the watchdog timer register definitions, hardware multiplier register definitions.
AD633-spice
- 模拟乘法器的PSPICE模型，可用于Multisim仿真等-PSPICE model of analog multiplier can be used Multisim simulation, etc.
mul64
- Verilog实现的64位乘法器，该乘法器是我所见过的最牛的乘法器、运算快、资源利用少-Verilog implementation of the 64-bit multiplier, the multiplier is the most I have ever seen cattle multiplier, computing faster, less resource utilization
Chapter10
- 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
costas的verilog程序
- costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
Verilog-float-mutiplier
- 32位浮点型乘法器，和开方器,很有用的一种，就是认真读懂-32 float mutiplier
mult_piped_8x8
- 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
vhdl_123
- 几个简单的vhdl程序。包括加法器，减法器，乘除法等等。-A few simple vhdl program. Including the adder, subtractor, multiplication and division and so on.
mult8_csdn
- 用verilog语言编写的8位乘法器，完成了8位二进制的整数乘法，供大家参考-Verilog language with 8-bit multiplier, completed the 8-bit binary integer multiplication, for your reference
mult
- 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
YCbCr_RGB_10bit
- YCbCr 转 RGB模块，以应用于项目中。 该模块可将10bitYCbCr分量视频转换为12bitRGB视频，需消耗乘法器。-YCbCr turn RGB module, to apply to the project. The module can be 10bitYCbCr component video converted to 12bitRGB video, need to consume multiplier.
LSD-TEST430F5438-01_V1.1StudyBoardInstructor
- 利尔达MSP430F5438学习板的中文资料,包含硬件链接,以及IO、UCS、FLASH、WDT、TimeA、TimeB、DMA、硬件乘法器、RTC、RAM、ADC12、UART、SPI、I2C、CRC等各种操作的试验代码。-利尔达board MSP430F5438 learning Chinese data, including hardware, links, and IO, UCS, FLASH, WDT, TimeA, TimeB, DMA, hardware multiplier, R