搜索资源列表
sequence_detector
- 序列检测器的设计师用Verilog语言实现的，实现了状态之间的有效处理，在FPGA开发板上可运行-module xulie_check(clk,rst,x,y) output y input clk,rst,x reg y reg [2:0] state parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7 always@(posedge clk or negedge rst)
serial1
- 基于VHDL语言实现的序列检测器，包含按键防抖动功能的实现。-Sequence detector based on the VHDL language, containing the button shake function to achieve.
The-VHDL-various-basic-code
- VHDL的各种基本代码 包括4选1,8选1多路选择器，8位全加器，加1减1计数器，序列检测器，异步清零16位加减可控计数器，数码管扫描程序，双2选1，状态机等基本程序！-VHDL basic code including 4 election 1,8 to 1 multiplexer selector, 8-bit full adder, plus 1 minus 1 counter sequence detector, asynchronous clear 16 plus or minus
xuliejianceqi
- 在FPGA开发板上用硬件描述语言实现一个状态序列检测器，比如边沿检测器等-FPGA verilog
11
- VHDL序列检测器，使用了EDA课程里面用到的状态机.-VHDL sequence detector, the use of EDA curriculum used inside the state machine.
SCHK
- ise13.2环境下VHDL编写的8位序列检测器+仿真波形-ise13.2 environment in VHDL 8 sequence detector+ simulation waveforms
seqdet_5
- 本程序是5位序列检测器的Verilog源代码,已经过上机运行检测。-This program is five sequence detector Verilog source code, has been detected on the machine running.
detseq
- verilog 序列检测器实例，检查输入数据中某一种序列是否出现-verilog sequence detector instance, check the input data, whether there is a particular sequence
Moore
- VerilogHDL语言实现的Moore 序列检测器-VerilogHDL language of Moore sequence detector
Mealy
- VerilogHDL语言实现的Mealy序列检测器-VerilogHDL language of Mealy sequence detector
verilog_prj_seq
- 序列检测器，检测序列“11010”，verilog HDL代码。-Sequence detector, detection sequence "11010", verilog HDL code.
sequential-detector
- 用状态机实现序列检测器的设计，并对其进行仿真和硬件测试-With a state machine sequence detector design, and its simulation and hardware testing
fsm_seq0101
- verilog状态机实现的序列检测器，本人仿真通过，绝对可用，欢迎大家下载学习。-verilog state machine sequence detector simulation by himself, absolutely free, welcome to download the study.
SCHK
- 10位序列检测器，有序列产生，分频器，按键消抖，序列检测，数码管扫描等几个模块构成，设计天津工业大学课程设计-10 sequence detector with sequence generation, dividers, key debounce, sequence detection, digital scanning, and several other modules, curriculum design, Tianjin Polytechnic University
Fsm
- 基于verilog的FSM设计，设计“101001”的序列检测器；包括testbench文件-The FSM based verilog design, design " 101001" sequence detector including testbench files
basic_1
- vhdl 语言实现序列检测器 -vhdl language sequence detector vhdl language sequence detector
XU-LIE-JIAN-CE-QI
- 用状态机实现序列检测器的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-State of mind achieved with a sequence detector source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
10010_xu_lie_jian_ce_qi
- 基于FPGA的序列检测器，能检测10010序列-FPGA-based sequence detector can detect a sequence 10010
10-sequence-detector
- 本系统采用实验箱的48MHz时钟作为输入时钟，将其分频得到计数器计数频率和序列检测器检测序列频率-The system uses a 48MHz clock experimental box as the input clock, to get the counter frequency divider and serial sequence frequency detector
bitdetect
- verilog代码编写110100序列的序列检测器，用状态机实现，包括仿真测试代码-verilog coding sequence detector 110100 sequence state machine implementation, including simulation test code