搜索资源列表
axis_fifo
- VIVADO下使用verilog编码的axi fifo的简单使用,仿真通过,供初学者学习。-Use the following VIVADO verilog coding axi fifo simple to use, through simulation, for beginners to learn.
rx_tx_demo
- 用verilog实现的少量字符串的连续收发,添加了FIFO模块,稍微修改下就可以使用。-Receive a small amount of a continuous string of verilog implementation, added FIFO module, can be used under slightly modified.
fifo_pipeline_booth_multiplier
- fifo_pipeline_modified_booth_multiplier一个使用FIFO的Booth乘法器,并且使用了流水线描述方式,本程序给予verilog 语言-fifo_pipeline_modified_booth_multiplier, a booth multiplier using pipeline technology in verilog HDL language
uart_server
- 24路串口转1路串口服务程序, 包括FIFO模块,串口接收,发送模块,定时器模块,检测控制模块等。采用Verilog编写-24 way serial ports to 1 serial port, including FIFO module,RX module,TX module, timer module, detection and control module, etc.. Verilog preparation
SD_Card
- sdhc卡spi扇区读verilog例程。包含sdhc卡初始化模块及一个扇区读模块,扇区读完数据放在一个fifo中缓存,为之后的工作做准备,可以集成到自己的项目中。已经在闪迪8Gsdhc卡上亲测成功-sdhc card sector read spi verilog routine. Initialization module and a read module contains sdhc card sector, the sector read data in a cache fifo in
asyn_fifo2
- 采用Verilog语言,使用FPGA内部IP核FIFO模块,实现串口的传输-Using Verilog language, the use of FPGA IP core internal FIFO module, serial data transmission
async_fifo
- 异步FIFO verilog 代码 复位到空,读侧以及写侧复位均可以使两侧同时复位,且基本同时放开。-ayschronized FIFO verilog code
uart_fifo
- 一份带有FIFO缓存的UART源码,采用verilog编写,实现批量数据的传输,数据缓存量可以通过修改源码中的FIFO的深度来改变。-This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.
fifofinal
- FIFO verilog学习时的基础编程练习。以8位输入,8位输出为例,输入输出采取不同时钟。 附加testbench。-first in first out
uartfifo
- 串口通信例程,使用FIFO数据缓存。Verilog源码,基于FPGA的uart开发,加深理解。-uart communication
parameter_uart_rx
- 串口接收模块,可以通过parameter,参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数,并根据缓冲的大小配置FIFO就可以使用。对帧错误(停止位不为高),检验错误和读FIFO超时(FIFO满的情况下,有新的数据到)等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data wi
oscillo_1
- 简单数字示波器的verilog设计,涉及到时钟同步,FIFO的配置和使用,非常适合用来学习FPGA以及熟悉quartus II 软件。(digital oscilloscope design)
uart_design
- UART设计的VERILOG代码,具有FIFO功能,能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)