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shujucaiji
- 基于单片机的数据采集系统，硕士论文 含PCB，单片机程序，CPLD程序-Microcontroller based data acquisition system, master' s thesis with PCB, microcontroller program, CPLD program
FPGA_design
- Altera+FPGA／CPLD设计基础篇和高级篇.pdf，详细讲解FPGA的设计过程及应用-Altera+ FPGA/CPLD Design Basics and advanced articles. Pdf, explain in detail the design process and application of FPGA
EPM570
- 这是ATLREA的EPM570的一个144管脚CPLD的最小系统图，对于设计CPLD的板子有作用-This is the EPM570 ATLREA a minimum of 144 pin CPLD system diagram, for the design of the board has the role of CPLD
modesim
- 讲述使用modelsim进行验证，使用verilogHDL语言进行建模。其中还包括一个讲述怎样用verilog语言编写测试台的详细文档，对fpga cpld设计的后期验证有很大的帮助。-About the use modelsim for authentication, use verilogHDL language modeling. It also includes a focus on how to use verilog test bench written a detailed doc
miniuart2
- 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a
Timer1
- F2407 有四个通用定时器，本程序主要对通用定时器1进行操作，1ms产生1 次中断，在中断中让2407＋CPLD开发板上的LED1发光二极管不断闪烁。 -F2407 has four general purpose timers, the program mainly to operate a general-purpose timer, 1ms interrupt generation 1, the interrupt to 2407+ CPLD development board fla
DA
- 00IC2407＋CPLD板上选用的DA转换器是TI公司的TLC5620,TLC5620是串行4通道8位 DA 转换器，DSP 通过 SPI 与其接口，TLC5620 的工作频率是 1MHZ,所有 DSP 的 SPI也必须设置位1MHZ, -00IC2407+ CPLD DA converter board is selected TI' s TLC5620, TLC5620 is a serial 4-channel 8-bit DA converters, DSP and its
AD
- 2407A 内置 16 通道10 位AD 转换器，在 00IC2407＋CPLD 实验板上只扩展两通道，分 别是第0 通道和第8通道，DSP 能承受的A/D 输入信号是0－3.3V，在00IC2407+CPLD 实 验板上没有单独采用基准源，直接使用系统的3.3V作为A/D 转换器的基准信号。 -Built-2407A 16-channel 10-bit AD converter, in 00IC2407+ CPLD experiment board extended only two
PCB_Project1.~(1).PrjPCB.Zip
- 51MCU & CPLD EZ-KIT实验开发板--
AlteraFPGACPLDcoder
- Altera FPGA/CPLD设计（基础篇）随书代码-Altera FPGA/CPLD design (fundamental) with the code book
AlteraFPGACPLDcoder2
- Altera FPGA/CPLD设计（高级篇）随书代码-Altera FPGA/CPLD Design (Senior Posts) With the written code
DSPandCPLD
- 基于DSP+CPLD的伺服控制卡的设计,资料很好，很不错，希望对大家有用。-Based on DSP+ CPLD design of the servo control card, data very good, very good, and I hope useful.
cpld
- 合肥零零电子提供的CPLD开发例程，主要是用C编写的-Hefei Hong development of electronic routines provided by the CPLD is mainly written using C
CPLD
- CCD开发板的CPLD图纸，使用XilinxCPLD，供大家参考-CCD CPLD development board drawings, with XilinxCPLD, for your reference
cpld
- CPLD 语言VHDL，实现对电机位置信号检测和输出驱动-CPLD language VHDL, to realize the motor position signal detection and output drive
Altera_FPGA_CPLD_Designing(Advanced)
- Altera FPGA_CPLD设计(高级篇) Altera FPGA/CPLD学习的优秀参考书-Altera_FPGA_CPLD_Designing(Advanced)
EPM240DemoBoard
- ALTERA CPLD EM240开发板原理图及源码-ALTERA CPLD EM240 development board schematics and source code
cpld_I2C
- CPLD+ARM的I2C通信，cpld上的I2C接收程序,内含仿真测试程序-I2C slave for cpld and ARM
Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex
- 来自于ALTERA官方网站。 本文档详细介绍怎样利用MAX® II CPLD 来实现脉冲宽度调制(PWM)。本设计还利用了MAX II CPLD 的内部用户闪存振荡器，不需要采用专门的外部时钟。 附有verilog源程序。-From ALTERA website. This document details how to use the MAX ® II CPLD to implement pulse width modulation (PWM). This design
Digital_Design_with_CPLD_Applications_and_VHDL_By
- Digital Design with CPLD Applications and VHDL (EBook)