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PWM_deadtime
- 利用HDL语言编写的PWM死区时间的实现，已经通过本人仿真验证，对于电力电子行业的研发人员有帮助-Using HDL languages implementation of PWM dead time has passed my simulation, for the power electronics industry, R & D staff to help
ps2_mouse_interface
- ps2接口的鼠标与vga接口的驱动程序，Verilog HDL语言，运用于FPGA-ps2_mouse_interface and vga in Verilog HDL language, applied to FPGA
spi93c46
- CPLD控制93C46的HDL示例代码，只是简易测试而已哦-CPLD control the 93C46 of the HDL sample code, just simple test just oh
Verilog
- 是摩托罗拉关于Verilog HDL的开发规范，相信对于学习Verilog程序设计的人会有很大的帮助-Motorola on the development of Verilog HDL specification, I believe that learning Verilog for programming will be of great help to people
HDB3_decode
- 用Verilog HDL语言进行HDB3译码，并通过Quartus Ⅱ仿真验证-With the Verilog HDL language HDB3 decoding, and simulation by Quartus Ⅱ
SPI_Slave
- SPI Slave example (VERILOG HDL)
60seconds
- 60秒秒表设计，可暂停和分段计数等，所有功能是利用verilog HDL来描述，最后下载到CPLD/FPGA才能运行。-60 seconds stopwatch design, may be suspended and the sub-count
sdram_control.RAR
- 基于XILINX FPGA的SDRAM 控制器代码。VERILOG HDL代码编写-SDRAM CONTROLER
iscas89_verilog
- Verilog HDL 时序基准电路 ISCAS89-ISCAS89 sequential benchmark circuits Verilog HDL
yibu_FIFO_design
- 异步FIFO实例，精通verilog hdl中的例子，供大家学习-Asynchronous FIFO instance, in the example verilog hdl proficiency for all learning
GFverilog-hdl
- 伽罗华域的乘法器的设计，使用有限域设计乘法器-Galois field multiplier design, the use of finite field multiplier design
yindaiao
- Verilog HDL语言，在FPGA开发板上实现电子琴弹奏的功能-Verilog HDL language, in the FPGA development board to achieve the functions of keyboard play
dds
- 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
RS-code
- 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
pal_vedio
- 基于FPGA的pal制模拟视频显示程序，verilog Hdl-pal-d vedio display fpga verilog
add_tree_mult
- 8位加法树乘法器,实现两个8位二进制数相乘，采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
i8255_verilog
- 8255的Verilog hdl源代码，适合FPGA工程师使用-8255' s Verilog hdl source code for FPGA engineers
FPGA_AD7822
- 基于FPGA的AD转换控制器设计，AD7822，quartus II，verilog hdl-A Design of the A/D Convertion Control Module Based on FPGA
8051_source_2.8a
- 8051内核的hdl代码，实际上是verilog格式不过上载页面只有一个vhdl选择，值得一读， 里面对仿真和验证的说明很有含金量-the hdl code of 8051 core
tftdot
- 我用verilog hdl写的tft lcd屏的控制程序，用来点亮屏上的任意点-I write the program in verilog hdl,it is used to control the tft lcd