搜索资源列表
verilog_sdram
- SDRAM读写控制的实现与Modelsim仿真,采用verilog HDL编写-sdram controller and simulate with modelsim
Coding-style-and-guidelines-of-HDL
- 该资料对数字设计的编码风格、编码规范给出了详细介绍，并简介了VHDL、verilog的编码要点。-The information on the coding style of digital design, coding specification gives a detailed descr iption and profile of VHDL, verilog coding points.
spi
- Verilog语言写的SPI接口（层次化设计，便于升级）-The implememt of SPI interface using Verilog HDL
Xilinx_FPGA_tutorial
- Xilinx ISE软件使用实例 Foundation入门 参数编辑 设计管理器/设计流程向导 FPGA editor 底层编辑器(floorplanner) 硬件调试器（hardware debuger) JTAG编程（JTAG Programmer) LogiBLOX Xilinx FPGA设计进阶 FPGAexpress的使用 Vertex器件结构 层次设计和同步电路设计 HDL设
Verilog-SRAM
- 用verilog hdl语言编写的fpga与片外sram 的读写控制-With the verilog hdl language fpga sram chip with read and write control
Sdram_Control_4Port
- SDRAM控制器HDL实现，sdram为美光公司的-sdram controller
32_bit_complex_multiplier
- 一款32位复数乘法器，用verilog写的。-32_bit complex multiplier,written in verilog HDL.
PS_2
- 此模块用于"PS/2接口的鼠标或键盘"与"具有外部读写的8位并口单片机"双向通信模块. Verilog HDL语言编写,在Quartus II 8.1 (32-Bit)软件中编译,并下载至EPM7128SLC84-10芯片中通过. 文件中有详细的注解. 此模块具有对于PS/2时钟和数据线的滤波功能,这样减少外部干扰，保证通信的可靠性！ -This module for the "PS/2 mouse or keyboard interface" and "read
ddsVHDL
- fpga实例 包含很多使用的例子 累加器 乘法器 触发器等-FPGA example real Verilog HDL
HDB3
- 用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试 -Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test
verilog
- Verilog 4*4查表法乘法器，应用广泛，速度快。-Verilog hdl。
Verilog-HDL-intra_prediction
- 基于H.264的帧内预测中4×4块的9种预测方法的源程序-H.264 intra prediction based on 4 × 4 block prediction method of the source 9
d_e_g_dds
- 基于Verilog HDL的迟早门码元同步方案中的DDS程序，已经仿真通过，可以在FPGA开发板上实现。迟-早门方式实现码元同步在无线通信中有着广泛应用。来自华中科大。-Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. F
cmultip
- 用VERILOG HDL 实现节省乘法器的16位复数乘法器-With VERILOG HDL achieve savings of 16-bit complex multiplier multiplier
counter
- 用Verilog HDL语言实现FPGA的频率等精度测量。（已经过验证）-Using Verilog HDL language, such as FPGA frequency measurement accuracy. (Has already been verified)
verilog
- 基于Verilog HDL的通信系统设计一书的电子教案，里面有很多例子，大家可以参考一下-Verilog HDL-based communication system design e-book lesson plans, there are many examples we can refer to
Verilog
- 基于Verilog HDL的通信系统设计一书的源代码，大家可以下载，参考一下-Verilog HDL-based communication system design of the book source code, you can download, refer to
i2c
- 标准I2c读写时序，verilog Hdl-Standard I2c read and write timing, verilog Hdl
softdrink_testbench
- 一种可应用于自动售货机的状态机的verilog HDL描述-Verilog HDL descr iption of a state machine used in vending machines
divider
- verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.